3-Share Threshold Implementation of AES S-box without Fresh Randomness
Takeshi Sugawara The University of Electro-Communications, Japan University of Michigan, US
This work is funded by JSPS KAKENHI Grant Number 17H06681 and JP18H05289
CHES 2019
1
3-Share Threshold Implementation of AES S-box without Fresh - - PowerPoint PPT Presentation
CHES 2019 3-Share Threshold Implementation of AES S-box without Fresh Randomness Takeshi Sugawara The University of Electro-Communications, Japan University of Michigan, US This work is funded by JSPS KAKENHI Grant Number 17H06681 and
This work is funded by JSPS KAKENHI Grant Number 17H06681 and JP18H05289
1
2
3
"# "% "& +# +% +& " +
Raw value Share Prob. (0,0,0) 1/16 (0,1,1) 1/16 (1,0,1) 1/16 (1,1,0) 1/16 1 (0,0,1) 3/16 1 (0,1,0) 3/16 1 (1,0,0) 3/16 1 (1,1,1) 3/16
4
xa xb xc ψa ψb ψc Xa Xb Xc xa xb xc ψa ψb ψc Xa Xb Xc
Remasking
Fresh randomness
5
!" !# !$ !" !# !$
x1
a
x1
b
x1
c
X1
a
X1
b
X1
c
x2
a
x2
b
x2
c
X2
a
X2
b
X2
c
X3
a
X3
b
X3
c
x0
c
x0
b
Sb Sa Sc Sb Sa Sc Sb Sa Sc x2
a
x2
b
x2
c
X0
b
X0
c
6
GF(24) GF(24) GF(24) GF(24) GF(22) GF(22) GF(22) GF(22) GF(22)
Mult.
Mult. Inv. Mult. Mult. Mult. Mult. 2nd Stage 3rd Stage 4th Stage
4 4 4 4 2 2 4 4 2 2 2 4 2 2 4 4 8 4 4
Linear Map Inv.
8
Linear Map
8
1st Stage
7
8
E
9
", !# ", !# "
E
a b c
a b c
E E E
10
!# !' !(
"
"
"
11
E
x
E R
ψ ψ ψ y X Y ⊥
⊥
ψ
" "# "$ "%
x
E R
ψ ψ ψ y X Y ⊥
⊥
ψ
" () ($ (*
x
E R
ψ ψ ψ y X Y ⊥
⊥
ψ xa xb xc
a b c
ψ ψ ψ ya yb yc Xa Xb Xc Ya Yb Yc
a b c
ψ ψ ψ
E E E a b c
ψ ψ ψ
R R R a b c
ψ ψ ψ
⊥ ⊥ ⊥
Converting unnecessary share to another one representing 0
13
, ,- ,. ,/
,$ ,& ,'
,$
.
,&
.
,'
.
,$
/
,&
/
,'
/
x1 x2 x3 X1 X2 X3 ψ ψ ψ ⊥ ⊥ ⊥
14
$ $ $
x1 x2 x3 X1 X2 X3 ψ ψ ψ ⊥ ⊥ ⊥ x1 x1 x1 x2 x2 x2 x3 x3 x3 X1 X1 X1 X2 X2 X2 X3 X3 X3
a b c a b c a b c a b c a b c a b c
Extra input Extra output
a b c
ψ ψ ψ
a b c
ψ ψ ψ
a b c
ψ ψ ψ
15
x1 x1 x1 x2 x2 x2 x3 x3 x3 X1 X1 X1 X2 X2 X2 X3 X3 X3
a b c a b c a b c a b c a b c a b c
Extra input Extra output
a b c
ψ ψ ψ
a b c
ψ ψ ψ
a b c
ψ ψ ψ
x1
a
x1
b
x1
c
X1
a
X1
b
X1
c
x2
a
x2
b
x2
c
X2
a
X2
b
X2
c
X3
a
X3
b
X3
c
x0
c
x0
b
Sb Sa Sc Sb Sa Sc Sb Sa Sc x2
a
x2
b
x2
c
X0
b
X0
c
16
x1 y1 z1 x2 y2 z2 x3 y3 z3 X1 Y1 g g Additional inputs for Additional outputs g g g g ⊥ ⊥ ⊥ ⊥ ⊥ ⊥ ⊥ ⊥ ⊥ the Changing of the Guards X2 Y2 X3 Y3 Z1 Z2 Z3 x1 y1 z1 x2 y2 z2 x3 y3 z3 X1 Y1 X2 Y2 X3 Y3 Z1 Z2 Z3
ga gb gc ga gb gc ga gb gc ga gb gc ga gb gc ga gb gc
17
18
2 2 2 2 2 2Split
4 4 4 2 2 2 8 8 8 2 2 2 8 8 8S-box input Additional input for GF(24) Additional input for GF(22) 2nd Stage 3rd Stage Linear Map 1st Stage
GF(22) mult GF(22) mult GF(22) mult GF(22) mult GF(22) mult GF(22) mult GF(24) mult,S-box output Additional output for GF(24) Additional output for GF(22) 4th Stage
GF(24) mult GF(24) mult GF(24) mult GF(24) mult GF(24) mult GF(24) mult 8 8 8 4 4 4 2 2 2Split Concatenate
4 4 48 bits 16 bits GF(22) Inv.
8 8 8xa xb xc ya yb yc za zb zc Xa
1 Xb 1 Xc 1Ya
1 Yb 1 Yc 1Za
1 Zb 1 Zc 1ta
1tb
1tc
1Xa
2 Xb 2 Xc 2Ya
2 Yb 2 Yc 2Za
2 Zb 2 Zc 2ta
2tb
2tc
2ta
3tb
3tc
3Xa
4 Xb 4 Xc 4Ya
4 Yb 4 Yc 4Za
4 Zb 4 Zc 4ta
4tb
4tc
4va vb vc wa wb wc Concatenate Xa
3 Xb 3 Xc 3Ya
3 Yb 3 Yc 3Za
3 Zb 3 Zc 3 4 4 419