The cross section of the ingot perpendicular to the axis is not perfectly circular. But we need circular wafers. So the ingot is ground to get a circular cross section. Subsequently wafers are sliced from the ingot using a wire saw. All the wafers are cut simultaneously. The edges of the wafer would be quite sharp. This can cause breakage of the wafer during handling. So the edge is rounded. All these processes are mechanical processes. An interesting point to note is that significant amount of silicon is lost during these processes. Especially the loss during sawing (kerf loss) is about 50 or more. Such high losses are not acceptable for solar cell manufacturing as the loss would increase the cost of the wafer which is a significant part of the total cost of the solar cells. Reduction of kerf loss by innovations in sawing process is an active field of research. Kerf loss is not a significant contributor to cost in VLSI as the value addition on the wafers by subsequent processing far exceeds the original wafer cost. 120
Wafer lapping, in addition to removing the bow and taper, the first process would also do a gross polish of the surface. This step is again a mechanical polishing step as none of the chemicals used would react with the wafer. Al2O3 would in the form of fine particles and is used as an abrasive. Subsequently the wafer is subjected to a nitride acid + HF treatment. This mixture etches silicon. Essentially HNO3 would oxidize the surface of the Si and the oxide would be etched by HF. The surface of the wafer would have been damaged mechanically during the previous processing steps. The etch is intended to remove the mechanical damage. The wafer surface is then subjected to a chemical mechanical polish (CMP). The wafer is placed on a flat platten and is subsequently polished using a slurry. The slurry compositions are trade secrets of the manufacturers. However they typically contain KOH or NaOH for etching of silicon and some micro and nano sized particles like SiO2 for mechanical polishing. The process may be carried out in several steps wherein the size of the particles used in the slurry is decreased in each subsequent step. The end result would be wafers with a mirror finish. Typically only one side of the wafer would be thus polished as the devices are made on only one side of the wafer. The other side would remain rough. However for specialized applications like in some MEMS devices and so on the wafer may have to be polished on both sides. Such wafers would be more expensive than single side polished wafers. An epitaxial layer of sufficient thickness may be grown on the top of the wafers. The devices may be eventually fabricated in such epitaxial films. 121
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SOI devices offer several advantages, the most prominent being the low drain and source capacitances. This can offer a favorable switching power versus delay relationship than typical MOSFETs. SOI devices have better radiation hardness. It is also an attractive substrate for some of the MEMS device fabrication as the oxide provides a good etch stop for silicon. We would not discuss the advantages of SOI devices in any great detail. Interested students can read any of the following books on SOI: 1. Jean-Pierre Colinge, Silicon-on-insulator technology, Materials to VLSI, 2 nd edition, Kluwer Academic Publishers, 1997 2. James B. Kuo and Ker-Wei Su, CMOS VLSI Engineering Silicon-on-insuator (SOI), Kluwer Academic Publishers, 1998 3. Sorin Cristoloveanu and Sheng Li, Electrical Characterization of Silicon-on-Insulator Materials and Devices, Springer International Series in Engineering and Computer Science, 1995. A typical SOI wafer is shown in the figure. It may be noted that the bottom part of the wafer is essentially for mechanical support. In state of the art SOI wafers for VLSI applications, both the bottom and the top parts are crystalline silicon. SIMOX process is mainly of historical importance. A heavy dose of oxygen, typically in the range of 1.8 x 10 18 ions of oxygen are implanted at 200 keV into the silicon wafer. During the implantation itself the wafer would be heated by energy transfer from the implanted species to the wafer. The wafer cas be easily heated to ~ 700 – 800 C. So the implanted oxygen precipitates during the implantation process itself. A continuous layer of SiO 2 is formed in the subsequent anneal step with good quality Si layer at the top. The process described above would result in ~ 200 nm of SiO 2 and 200nm of Si on top. A draw back of the process would be potentially high concentration of oxygen in the top layer, defects at the SiO 2 – Si interfaces, long time for implantation process as the dose is quite high and long anneal times. Similar processes can be used for the manufacture of SIMNI (Separation by IMplanted NItrogen) and SIMON (Separation by IMplanted Oxygen and Nitrogen) wafers. 123
The smart cut process is depicted on the slide. The process starts with two wafers as shown. The “green” wafer would provide the mechanical support in the eventual SOI wafer and is known as the handle wafer. The color is just to distinguish the two wafers from each other. Wafer A is cleaned and oxidized to the desired thickness. Subsequently a high dose hydrogen implant is given on the surface of the wafer A. The dose is in the range of 5 x 10 16 cm -2 . Such a heavy dose would result in microcavities and bubbles at a depth equal to the range of implantation. The wafers are subsequently cleaned so that the surfaces to be bonded together are made hydrophilic. Subsequently hydrophilic bonding is carried out. Cleaned surface of SiO 2 would contain Si-OH bonds. There would be also H 2 O adsorbed on the SiO 2 surface. The interaction between the adsorbed water and the Si-OH groups would result in bonding between the wafers. Subsequently the wafer is annealed at ~ 500C. Two processes happen during this process: 1. The bonding is strengthened by heating the wafer at ~ 700 C, the following reaction happens at the interface between the two wafers: Si-OH + OH-Si => Si-O-Si + H 2 O. This result in strong bonding between the two wafers. 2. The size of the microcavitiesincrease and the wafer would cleave parallel to the bonding surface. This results in an SOI wafer and the original wafer A with slightly lower thickness and more surface roughness. This can be used again for making more SOI wafers. The SOI wafer is further annealed at 1100C. The water produced can be used for further oxidation of the handle wafer by annealing at a higher temperature. This would further strengthen the bond. 124 The surface of the SOI wafers would be rough as it cleaved by joining together of microcavities. The wafers surface is subsequently subjected to chemical mechanical polishing to obtain smooth mirror finish surfaces.
Poly or multi crystalline silicon is an attractive option for solar cell fabrication. The reasons are many fold. The cost of cell and hence the cost of electricity produced is the most important impediment to large scale deployment of solar cells for energy harvesting. The single junction silicon solar cell process is rather simple compared to the VLSI chip fabrication. Once you have the wafer, less than 10 process steps are enough to complete the cell. On the other hand the VLSI chip fabrication is much more complex and the number of process steps can run into several hundreds. This means that the value addition on a wafer during solar cell manufacturing is smaller than in a VLSI chip manufacturing process. As a consequence the wafer cost is a significant fraction of the total cost of a solar cell. So there is a significant drive to reduce the cost of the wafers by innovative crystal growth processes and by reducing kerf loss. The solar cell efficiency is impacted by the life time of minority carriers in the material and hence the quality of the silicon used. Record efficiency solar cells (>22 % efficiency) are made on FZ wafers and are very expensive due to the high cost of wafers and complex processing. On the other hand 15% efficiency large area cells can be fabricated using multi crystalline wafers and the cost works out much lower than technologies based on costlier wafers. Multi crystalline is produced in a variety of ways. We would only discuss one of the techniques, called the travelling heater method. The technique is a variant of Bridgman technique. Since the grain boundaries between Silicon grains have large number of recombination centers, it is desirable to have large grain sizes so that the grain surface area to the volume of the wafer is low. Also vertically oriented grains are desirable so that electrons and holes do not encounter grains during diffusion to the respective collecting electrodes. Poly-Si chunks are melted in a furnace as shown above at about 1550C. An important distinction here is that the silicon would freeze inside the crucible unlike in a CZ process. In principle the melt can be cooled to obtain a block of poly-Si. However the grains would be randomly oriented. To grow vertically aligned grains, the melt is cooled from the bottom by moving the heater assembly up as shown on the plot on the right. 125
The graph shows the temperature of the heaters and the bottom of the crucible as a function of time. The image on the right shows the cross section a poly-Si block fabricated by the technique. Vertically oriented crystalline grains are visible. The block is subsequently sliced by the wire saw method we had seen on a previous slide. 126
Unlike the VLSI wafer, the surfaces of the wafers used in solar cell manufacturing are not polished. This is because the surface of the silicon would be intentionally textured to reduce reflections from the surface of the cell. 127
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