What Shall We Do? Let's design a simple processor to understand the - - PowerPoint PPT Presentation

SLIDE 1

17.1

Unit 18

Processor Organization

17.2

What Shall We Do?

• Let's design a simple processor to understand

the entire flow from writing software to designing the hardware

– This may not be the most advanced processor but the goal is to give you a fully working example from software to hardware

17.3

The Instruction Set (1)

• To start we will define the instruction set
• Let's make this a simple calculator-like processor that can

perform at least the following 3 operations:

– ____ – ____ – ____

• Goal is to evaluate simple arithmetic expressions: (7+4-5)&3
• Let's use __-bit data values (i.e. all data operands will be __-bits)
• To keep the number of bits needed to code an instruction to a

minimum, let's use an ______________________ architecture where the _____ register is always one ________________

– ADD 7 means: ____________ – SUB 5 means: ____________

17.4

The Instruction Set (2)

• Let's assume the output of this computer is just 4 LED's

to display a 4-bit binary number

• We'll provide some additional instructions to help us

perform the calculations:

– ______________________ – ______________________ – ______________________

• That leaves us with 6 total instructions

– How many bits do we need for the opcode of our instructions? __________

• If we want to store data/constants in our instructions

(e.g. ADD 7, SUB 5) how many additional bits do we need in our instruction? ____________

• Instructions need __ opcode + ___ data bits = __-bits

– Let's round up to 8-bits for each instruction

Output LEDs (Display = 7 = 01112)

Opcode (3-bits)

Unu sed

Constant (4-bits)

Chosen Instruction Format Computer System

SLIDE 2

17.5

Compilation

• Consider the following "high-level" code

– (7 - 4 + 6) & 3

• "Compile" it to an appropriate instruction

sequence (i.e assembly)

– Assembly refers to the human readable syntax

• f each instruction
• Now we need to convert to binary…

Instruction Set Summary

• ADD k (ACC += k)
• SUB k (ACC -= k)
• AND k (ACC &= k)
• LOAD k (ACC = k)
• CLR (ACC = 0)
• OUT (OUT = ACC)

17.6

Defining the Machine Code

• Machine code refers to the ____________

representation of each instruction.

• We first need to define the actual opcodes so

we can translate the assembly you wrote on the previous slide into binary for the hardware to execute

• Before we do that, let's consider the hardware

design as this will help us choose appropriate

• pcodes

17.7

Arithmetic and Logic Units

• Let's define and design the ALU that will

perform the various operations our computer should support plus a few extra…

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

F[2:0] Op./Result 000 R = X + Y 001 R = X - Y 010 R = X 011 R = Y - X 100 R = X & Y 101 Unused 110 R = 0 111 Unused

We will design what is inside this block. We just made up these code assignments and the various operations. Remember, we definitely need to support ADD, SUB, AND, and CLR (R=0). 17.8 A0 A1 A2 A3 B0 B1 B2 B3 4-bit Binary Adder C0 C4 S0 S1 S2 S3 S I0 Y I1 2-to-1, 4-bit wide mux X0 X1 X2 X3 Y0 Y1 Y2 Y3 R0 R1 R2 R3 F0 F1 F2 S I0 Y I1 2-to-1, 4-bit wide mux S I0 Y I1 2-to-1, 4-bit wide mux X0 X1 X2 X3 Ci=________ S1 = ______ S2 = ______ S3 = ________ EE109 ALU

EE109 ALU

S I0 Y I1 2-to-1, 4-bit wide mux S0 = ______

Blank ALU To Complete

F[2:0] Op. F[2:0] Op. 000 R = X + Y 100 R = X & Y 001 R = X - Y 101 Unused 010 R = X 110 R = 0 011 R = Y - X 111 Unused

SLIDE 3

17.9

Control Logic

• S0 =
• S1 =
• S2 =
• Ci =
• S3 =

R FS[2:0] S0 S1 S2 Ci S3 X+Y 000 X-Y 001 X 010 Y-X 011 X & Y 100 unused 101 110 unused 111

1 00 01 11 10 F0 F2F1 d d 1 1 d 1 00 01 11 10 F0 F2F1 d d d 1 1 00 01 11 10 F0 F2F1 d 1 d 1 d 1 00 01 11 10 F0 F2F1 d d 1 1 1 00 01 11 10 F0 F2F1 d d 1 S0 S1 S2 Ci S3

17.10 A0 A1 A2 A3 B0 B1 B2 B3 4-bit Binary Adder C0 C4 S0 S1 S2 S3 S I0 Y I1 2-to-1, 4-bit wide mux X0 X1 X2 X3 Y0 Y1 Y2 Y3 R0 R1 R2 R3 F0 F1 F2 S I0 Y I1 2-to-1, 4-bit wide mux S I0 Y I1 2-to-1, 4-bit wide mux X0 X1 X2 X3 S1 = F1• F0' S2 = F1'•F0 S3 = F2 EE109 ALU

EE109 ALU

S I0 Y I1 2-to-1, 4-bit wide mux S0 = F1•F0 Ci=F0

Completed ALU

F[2:0] Op. F[2:0] Op. 000 R = X + Y 100 R = X & Y 001 R = X - Y 101 Unused 010 R = X 110 R = 0 011 R = Y - X 111 Unused

17.11

Aside: Impacts of Coding (1)

• What if we changed the codes used for each
• peration?

F[2:0] Op./Result 000 R = X + Y 001 R = X - Y 010 R = X 011 R = Y - X 100 R = X & Y 101 Unused 110 R = 0 111 Unused

We just made up these code assignments and the various operations. Remember, we definitely need to support ADD, SUB, AND, and CLR (R=0).

F[2:0] Op./Result 000 R = X + Y 001 R = Y - X 010 R = X - Y 011 R = 0 100 R = X 101 R = X&Y 110 Unused 111 Unused

17.12

Aside: Impacts of Coding (2)

• S0 = F2'F0
• S1 = F2F0' + F1F0
• S2 = F2F0' + F2'F1'F0
• Ci = F1+F0
• S3 = F1F0 + F2F0

R FS[2:0] S0 S1 S2 Ci S3

X + Y

000

Y - X

001 1 1 1

X - Y

010 1 1 011 d 1 d 1

X

100 1

X&Y

101 d 1

Unused

110 d d d d d

Unused

111 d d d d d

1 d 1 00 01 11 10 F0 F2F1 d 1 1 d d 1 00 01 11 10 F0 F2F1 d d 1 d 1 00 01 11 10 F0 F2F1 d 1 1 1 d d 00 01 11 10 F0 F2F1 d 1 d 1 00 01 11 10 F0 F2F1 d 1 1

Notice how much more logic this coding yields.

SLIDE 4

17.13

Defining the Machine Code Format

• Using the ALU design can you suggest opcodes for the various

instructions?

– The accumulator (ACC) will be connected to the result of the ALU – But should the ACC be connected to the X or Y input of the ALU?

• Important: We achieve Load by passing __ through the ALU to the ACC, so we need

the constant to come in on X (so ______ cannot) F[2:0] Op./Result 000 R = X + Y 001 R = X - Y 010 R = X 011 R = Y - X 100 R = X & Y 101 Unused 110 R = 0 111 Unused Instruc. OPCODE Op./Result 000 001 010 011 100 101 110 111 Instruction Set Summary

• ADD k (ACC += k)
• SUB k (ACC -= k)
• AND k (ACC &= k)
• LOAD k (ACC = k)
• CLR (ACC = 0)
• OUT (OUT = ACC)

+ =

17.14

Assembler

• Now translate the assembly you

found from a few slides back to machine code and show it as 2 hex digits per instruction

• The "high-level" code was

– (7 - 4 + 6) & 3

• "Compile" it to an appropriate

instruction sequence (i.e assembly)

– CLR = ______ – ADD 7 = ______ – SUB 4 = ______ – ADD 6 = ______ – AND 3 = ______

Opcode (3-bits)

Unu sed

Constant (4-bits)

Chosen Instruction Format

Instruc. OPCODE Op./Result ADD 000 ACC = ACC + C OUT 001 OUT = ACC LOAD 010 ACC = C SUB 011 ACC = ACC - C AND 100 ACC = ACC & C

• 101

Unused CLR 110 ACC = 0

• 111

Unused

17.15

Processor Datapath

• Now let's consider the processor data path

Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

Control

LEDs

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

Control

LEDs

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0]

17.16

Sample Execution of SUB 11

Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

Control

LEDs

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7 OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7 OUT_LD

I7 I6 I5

ACC_LD

I7 I6 I5

ACC_LD

I7 I6 I5

• r

1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

SLIDE 5

17.17

A Problem

• Write assembly for:

– ((7 & 3) + (6 & 5))

• ____________________________

17.18

A Solution

• Let's modify our processor as follows:

– Add _______________ for temporary storage: ________________

• Could add more but we'll keep it simple

– A new instruction to save the ______ to a register: SAVE Rx (_______________) – Update ALU instructions to be able to specify a _________________ rather than just a constant ADD Rx (ACC = ACC + Rx) SUB Rx (ACC = ACC - Rx) AND RX (ACC = ACC & Rx) LOAD Rx (ACC = Rx) – Update the instruction format to use the leftover bit to indicate whether the operand is a constant or should come from a register

Opcode (3-bits) Constant (4-bits) Opcode (3-bits)

New Instruction Format

Unused (3-bits)

17.19

Updated Assembly

• Write assembly for:

– ( (7 & 3) + (6 & 5) )

• New assembly & machine code

Opcode (3-bits) C/R Constant (4-bits) Opcode (3-bits) C/R 1 Unused (3-bits) Reg 0/1

New Instruction Format

Instruc. OPCODE Op./Result ADD 000 ACC = ACC + C/R OUT 001 OUT = ACC LOAD 010 ACC = X SUB 011 ACC = ACC - C/R AND 100 ACC = ACC & C/R

• 101

Unused CLR 110 ACC = 0 SAVE Rx 111 Rx = ACC

17.20

Updated Processor Datapath

D[3:0] Q[3:0] EN CLK D[3:0] Q[3:0] EN CLK Data Registers ACC[3:0] R0_LD R1_LD CLK CLK Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

S I0 Y I1 2-to-1, 4-bit wide mux

Control

R0 R1

______

LEDs R0[3:0] R1[3:0]

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] D[3:0] Q[3:0] EN CLK D[3:0] Q[3:0] EN CLK Data Registers ACC[3:0] R0_LD R1_LD CLK CLK Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

S I0 Y I1 2-to-1, 4-bit wide mux

Control

R0 R1

LEDs R0[3:0] R1[3:0]

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] OUT_LD

I7 I6 I5

ACC_LD

I7 I6 I5

SLIDE 6

17.21

More Practice (On Own Time)

• Write assembly for:

– ( (4&14) + (5&3) - (6&11) + (8&13))

• Try to use as few instructions as you can

Opcode (3-bits) C/R Constant (4-bits) Opcode (3-bits) C/R 1 Unused (3-bits) Reg 0/1

New Instruction Format 17.22

D[3:0] Q[3:0] EN CLK D[3:0] Q[3:0] EN CLK Data Registers ACC[3:0] R0_LD R1_LD CLK CLK Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

S I0 Y I1 2-to-1, 4-bit wide mux S I0 Y I1 2-to-1, 4-bit wide mux

Control

R0 R1

I0 I4

LEDs R0[3:0] R1[3:0] R0_LD

I0

R1_LD

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7 OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7

I7 I6 I5 I0 I7 I6 I5

OUT_LD

I7 I6 I5

ACC_LD

I7 I6 I5

ADD 7

1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 0101 0000 0000 1

17.23

D[3:0] Q[3:0] EN CLK D[3:0] Q[3:0] EN CLK Data Registers ACC[3:0] R0_LD R1_LD CLK CLK Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

S I0 Y I1 2-to-1, 4-bit wide mux S I0 Y I1 2-to-1, 4-bit wide mux

Control

R0 R1

I0 I4

LEDs R0[3:0] R1[3:0] R0_LD

I0

R1_LD

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7 OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7

I7 I6 I5 I0 I7 I6 I5

OUT_LD

I7 I6 I5

ACC_LD

I7 I6 I5

ADD R0

1 0 0 0 1 1 1 1 1 1 1 1 1 0101 0100 0000 1 1

17.24

D[3:0] Q[3:0] EN CLK D[3:0] Q[3:0] EN CLK Data Registers ACC[3:0] R0_LD R1_LD CLK CLK Instruction Fetch Logic CLK 5-bit Counter CLR Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 32x8 Memory I0 I1 I2 I3 I4 I5 I6 I7 CLK RESET Q4 A4

S I0 Y I1 2-to-1, 4-bit wide mux S I0 Y I1 2-to-1, 4-bit wide mux

Control

R0 R1

I0 I4

LEDs R0[3:0] R1[3:0] R0_LD

I0

R1_LD

X0 X1 X2 X3 Y0 Y1 Y2 Y3 EE109 ALU R0 R1 R2 R3 F2 F1 F0

ACC_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 ACC[3:0] OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7 OUT_LD CLK EN CLK D3 D2 D1 D0 Q3 Q2 Q1 Q0 OUT[3:0] I5 I6 I7

I7 I6 I5 I0 I7 I6 I5

OUT_LD

I7 I6 I5

ACC_LD

I7 I6 I5

SAVE R1

1 x 1 1 1 0 0 0 1 1 1 1 1 x x x x x x x x 1 1 0101 0000 0000 1 1