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Welcome to the Atomic Scale Era: New Paradigms and Processes for Continued Scaling May 12, 2017 Robert D. Clark Senior Member of the Technical Staff TEL Technology Center, America, LLC TEL TECHNOLOGY CENTER, AMERICA, LLC. LEADING-EDGE

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May 12, 2017 Robert D. Clark Senior Member of the Technical Staff TEL Technology Center, America, LLC

Welcome to the Atomic Scale Era: New Paradigms and Processes for Continued Scaling

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Robert D. Clark/ TTCA-TFPT / 05122017.01 2

TEL TECHNOLOGY CENTER, AMERICA, LLC.

LEADING-EDGE R&D CAPABILITY

The SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s Albany NanoTech Campus New Zero Energy Nanotechnology (ZEN) Building

2003 04 05 06 07 08 09 10 11 12 13 14 15

TTCA* Founded NanoFab South Annex

13 TEL tools in a 4000+ sq ft cleanroom

NanoFab South

6 TEL tools in a 2000+ sq ft cleanroom

NanoFab North

40 TEL tools in a 4000+ sq ft cleanroom

First MOSCAP Data First Full Flow Transistor Data First Full Flow FinFET Data NanoFab Central

18 TEL tools in a 4000+ sq ft cleanroom

New Fab NFX

50,000 sq ft cleanroom 300/450mm compatible 3 TEL tools installed

First III-V Data First DSA Data 1.6nm LER w/DCS and NTD First 7nm MIS contacts First Si ALE DCS Enabled LFLFLE Solid Source Fin Doping 7nm SiN/SiO2 ALE A WORLD-CLASS TEAM

90+ engineers 60+ service/support

INTEGRATED PROCESSING – TEL TOOLS

Coater/Developer Tools FEOL/BEOL Tools Metrology/Test Tools 12 42 26

LITHOGRAPHY ACCESS

ASML 1700i 1.2NA/50nm l/s ASML 1950i 1.35NA/35nm l/s ASML NXE3300B 0.33NA/18nm l/s

A B C D E E A B C D

TEL is a registered trademark or a trademark of Tokyo Electron Limited in Japan and /or other countries

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Robert D. Clark/ TTCA-TFPT / 05122017.01 3

  • Background
  • Technology and Scaling Trends
  • Patterning Challenges and Approach
  • Process technology examples
  • New Directions for High K Materials
  • New Contact Structures
  • Summary

Outline

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Robert D. Clark/ TTCA-TFPT / 05122017.01 4

Background

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Robert D. Clark/ TTCA-TFPT / 05122017.01 5

Welcome to the Atomic Scale Era- There’s No Longer Plenty of Room at the Bottom.

Historical and Projected Atomic Feature Sizes (half pitch/0.235 nm/Si atom) in CMOS High Volume Manufacturing. Projected feature sizes are based on Intel historical trend through 14nm manufacturing.

Projected 10nm 10nm Actual* CGP 54 54 MX 43 36 Fin 33 34

*Mistry Intel TMD March 28, 2017

Scaling is Taking Longer… But So Far it is Still Delivering.

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Robert D. Clark/ TTCA-TFPT / 05122017.01 6

So What Happens When We Run out of Room at the Bottom? We Do What We’ve Always Done: We Go Up

Source: dailymail.co.uk

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Robert D. Clark/ TTCA-TFPT / 05122017.01 7

Technology and Scaling Trends

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Robert D. Clark/ TTCA-TFPT / 05122017.01 8

180 130 110 90 65 45 32 22 14 10 7 5 1 10 100 1000 1990 1993 1996 1999 2002 2005 2008 2011 2014 2017 2020

Technology Trend: Going Vertical

Vertical utilization is the key approach towards sub-10nm generation

Resolution Wavelength

i-Line ArF EUV

High AR of DRAM 3D NAND large stack Planar FinFET Nano-wire

immersion

3D Architecture Scaling

KrF

[nm]

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Robert D. Clark/ TTCA-TFPT / 05122017.01 9

Scaling Trend – Sub-lithographic Patterning

Complex and fine patterning technology is required for further scaling

20 40 60 80 100 20 40 60 80 100

  • Min. Metal Pitch (nm)

Contacted Gate Pitch (nm)

SADP SADP SE SAQP EUV SE

N22 N10 N7 N5 Metal Pitch Poly Gate Pitch

193i

N14

Design layout change from 2D to 1D

1 mask 1 mask (SAMP) n masks

Alignment challenge CD challenge

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Robert D. Clark/ TTCA-TFPT / 05122017.01 10

Technology Trend: Self-(Something) Revolution

Mircea and Hsu MPT Short Course SPIE 2015 Auth VLSI 2014

Younkin SPIE 2015 Self-Aligned Double Patterning Self-Aligned Contact

Säynätjoki 8 May 2012, SPIE Newsroom. DOI: 10.1117/2.1201204.004218

Atomic Layer Deposition Atomic Layer Etching

Kim JES EDL 158, 12, 2011, D710-4 doi: 10.1149/2.061112jes

Self-Aligned Self-Directed Self-Limited

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Robert D. Clark/ TTCA-TFPT / 05122017.01 11

Patterning Challenges and Approach

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Robert D. Clark/ TTCA-TFPT / 05122017.01 12

Self-Aligned Multi-Patterning (Example 193i based SAQP)

𝜏𝐹𝑄𝐹 = (𝜏𝐷𝐸−1 2 )2= (1 2)2 = 𝟏. 𝟔 𝒐𝒏

  • 1. Grid Litho
  • 2. 1st Core Etch
  • 3. 1st Spacer

Depo

  • 5. 2nd Core

Etch

  • 6. 2nd Spacer

depo

  • 7. 2nd Mandrel

Pull

  • 4. 1st Mandrel

Pull

Adapted from Mohanty and Smith SPIE 2017

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Robert D. Clark/ TTCA-TFPT / 05122017.01 13

Patterning challenges to EPE

SAQP Line cutting with LELELE Final Pattern

𝐹𝑄𝐹 = 𝑔(CD variation, Pattern OL)

  • Mandrel, spacer, cuts
  • Traditional sources of CD variation
  • Roughness
  • Previous Pattern
  • Cuts to the grid
  • Cuts to each other

EPE control is critical for further extension

(EPE : Edge Placement Error)

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Robert D. Clark/ TTCA-TFPT / 05122017.01 14

Bottom-Up Lithography Top-Down Lithography

Patterning paradigm towards placement accuracy

The paradigm is expanding to self-alignment and bottom up approach Multiple Patterning Self-Alignment

LEx

Multi color

SAMP

ALD / ALE

Shorter Wavelength

Immersion EUV i-line KrF ArF

Self-Alignment + Self-Assembly

Selective Deposition DSA

Shrink

+ +

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Robert D. Clark/ TTCA-TFPT / 05122017.01 15

Patterning Challenges and Approaches

Typical Scheme Challenge Potential Approach Grid formation SADP SAQP LER, LWR, local CDU

  • Etch smoothing (DCS)
  • Spacer reshape

Spacer leaning

  • Dep / cure and trim

Cost

  • PR mandrel

Cut / Block LEx CD, CDU, CER

  • Healing, shrink

Alignment with grid (within layer)

  • SAB

Cost and complexity mitigation

  • EUV

Via/Contact formation LEx CD, CDU, CER

  • Healing, shrink

Alignment with metal lines (inter layers)

  • FSAV, SAC, SAGC

Cost and complexity mitigation

  • EUV

New process development Atomic level process

  • ALE / ALD

Bottom up lithography

  • Selective deposition

Self- Something

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Robert D. Clark/ TTCA-TFPT / 05122017.01 16

Process Technology Examples

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Robert D. Clark/ TTCA-TFPT / 05122017.01 17

Self-alignment through etch selectivity

Intended Design Conventional approach

(using L/S grid)

Etch selects mandrel Etch selects fill material

A = Mandrel B = Spacer C = Fill material Self-aligned approach

(using three grid colors)

C B A C B B A C B B A C B

self-alignment of cut/block is enabled by SAB, using etch selectivity

SAB (Self-aligned Block)

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Robert D. Clark/ TTCA-TFPT / 05122017.01 18

EPE margin improvement by SAB

12 12

Conventional SAB

half pitch 36 36 etch etch half pitch

(pitch assumption : 24nm)

EPE margin of hard mask is 3 times relaxed

Lithography OL limit will be covered within the margin Lithography OL is restricted to be within 6nm (regardless of 193i or EUV)

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Robert D. Clark/ TTCA-TFPT / 05122017.01 19

Gate Stack with 2 hole masks

Self-alignment to gate cap, gate spacer and ILD

Multi-color approach enabling Self-alignment Gate Gate Gate Spacer Gate Spacer Gate Spacer Gate Spacer

Gate cap Gate cap

ILD Gate Gate Gate Spacer Gate Spacer Gate Spacer Gate Spacer

Gate cap Gate cap

ILD GC MD MD GC GC Open

EPE Improvement through Self-Aligned Gate Contact (SAGC)

Adapted from Mohanty and Smith SPIE 2017

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Robert D. Clark/ TTCA-TFPT / 05122017.01 20

Bottom-up lithography

Selective Deposition DSA < Metal on Metal > < Dielectric on Dielectric >

D M M M M M M

growth

D D D D M M M D D D

growth

D D D D M M M M

growth

D D D D

L/S Pitch Multiplication Hole Pitch Multiplication

Bottom-up lithography enables self-alignment and self-assembly

D : Dielectric M : Metal LKR : Low-k Restoration self-assembly DSA : Directed Self-Assembly

x4 multiplication capable at 30nm pitch x3 multiplication capable at 30nm pitch

Clark AVS 2015

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Robert D. Clark/ TTCA-TFPT / 05122017.01 21

Selective deposition: Metal on Metal

50nm

106.9nm CD: 46.4nm

6.2nm

W Ru 200nm

EDX mapping X-TEM

Ru 37.7nm 41.7nm

SiO2 W Ru

growth

SiO2 W Ru

growth

Deposition of Ru is demonstrated to grow on W only

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Robert D. Clark/ TTCA-TFPT / 05122017.01 22

New Directions for High K – Teaching a New Dog Old Tricks

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Robert D. Clark/ TTCA-TFPT / 05122017.01 23

Selective deposition: Dielectric on Dielectric (Al2O3 on TOX, not on Si)

SPA H plasma effective in suppressing Al2O3 growth up to ~5nm on Si and not on oxides

Si Substrate Treatment:

  • HDHD: cyclical deposition and low-temperature

plasma hydrogen (SPA H) treatment

  • Sustained H-termination on Si
  • Delayed ALD Al2O3 incubation

4-5nm selectivity

10:1 Thickness

HDHD

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Robert D. Clark/ TTCA-TFPT / 05122017.01 24

Anisotropic atomic layer etching of high K films

BCl3 Ar Plasma 1 cycle

Min Microelectronic Eng. 110 (2013) 457–460 50 40 30 20 10

2 4 6 8

ALE cycle (#) Amount etched (Å)

10 12 14

ER=4Å/cycle Al2O3

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Robert D. Clark/ TTCA-TFPT / 05122017.01 25

Al2O3 HfO2

Area Selective Deposition by Combining ALD and Etching

ALD High K Dielectrics followed by Anisotropic Etching enables Ultra- Thin ALD Sidewall Spacers

Note: Very good selectivity to SiO2

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Robert D. Clark/ TTCA-TFPT / 05122017.01 26

Ferroelectric HfZrO

Adapted From: Sonal Day et. al. FCNM 2017 Also See: Sharma et. al. VLSI 2017 accepted - coming to Kyoto in June 5nm TiN/7nm Hf0.2Zr0.8O2/Si + 700 oC 30 sec. PMA

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Robert D. Clark/ TTCA-TFPT / 05122017.01 27

New Contact Structures

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Robert D. Clark/ TTCA-TFPT / 05122017.01 28

For Thin Body and Fin Structures MIS contact should have an area advantage over silicide

Paramahans VLSI 2012

Rc = ρc/A Planar Bulk Thin Body/Fin Asilicide > AMIS Asilicide < AMIS

Area Effects – Contacts -Theory

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Robert D. Clark/ TTCA-TFPT / 05122017.01 29

  • Wrap Around Contacts are proposed to provide an area advantage for

Metal/Semi contacts formed within M0

  • MIS Contacts and Direct Metal Contacts enable the use of a WAC scheme

– NiPtSi contacts require PVD (poor conformality)

Wrap Around Contacts (WAC)

PFET bottom coated

Wrap Around Contacts

More Info? See “Ultralow Resistive Wrap Around Contact to Scaled FinFET Devices by using ALD-Ti Contact Metal” S.A. Chew et. al.

  • Accepted. IITC May 16, 2017 Hsinchu, Taiwan.
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Robert D. Clark/ TTCA-TFPT / 05122017.01 30

Implant?- Conformal solid source doping by ALD

Successful use of ALD B2O3 to create shallow dopant wells by thermal diffusion into Si

  • demonstrated. ALD BN did not diffuse

indicating it could be an in-situ cap layer.

Consiglio ALD 2014 and Consiglio JVSATA 34, 01A102 (2016); doi: 10.1116/1.4928705

Before anneal After anneal

Example Application: Punch through stopper for 14nm FinFET is made by SSD

Natarajan IEDM 2014

B2O3 vs. BN with anneal – B profile

180 160 140 120 100 80 60 20 40 60 80

B2O3 ALD cycles Rs (Ohms/sq)

Anneal N2, 30 secs

900˚ C 1000˚ C

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Robert D. Clark/ TTCA-TFPT / 05122017.01 31

Summary

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Robert D. Clark/ TTCA-TFPT / 05122017.01 32

  • 3D Architectures and Scaling are Required for 10nm and beyond Scaling
  • Meeting the challenge of 3D, EPE, New Devices and Contacts Requires New Process

Technology and Patterning Paradigms

  • TEL is working continuously to develop and improve the New Processes needed to

continue scaling beyond the 10nm node and through the next decade.

Summary

NS300Z

TELINDY PLUSTM

TactrasTM VigusTM

Certas LEAGATM

NT333TM

CLEAN TRACKTM LITHIUS ProTM Z CELLESTA

TM-i

Triase+ TM

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Robert D. Clark/ TTCA-TFPT / 05122017.01 33

  • TTCA R&D, Operations and Equipment Support Teams: Kanda Tapily, Steve

Consiglio, Kyle Yu, Danny Newman, Dave O’Meara, Jeff Smith, Cory Wajda, Gert Leusink

  • CNSE: Professor Alain Diebold’s Group – Ferroelectric HfZrO
  • Notre Dame: Professor Suman Datta’s Group – Ferroelectric HfZrO
  • IMEC: MOL Contacts Team, especially S.A. Chew H. Yu and M. Schaekers –

Wrap Around Contacts

  • TEL Japan staff including H. Yaegashi, M. Honda and T. Tsunomura for

support and assistance on patterning and selective deposition materials

  • Tokyo Electron America Staff including M. Somervell and B. Rathsack for

assistance on patterning and DSA materials

Acknowledgement

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Robert D. Clark/ TTCA-TFPT / 05122017.01 34

  • Clark, R.D. Materials 2014, 7(4), 2913-2944; doi:10.3390/ma7042913
  • Clark, R.D. 2015 American Vacuum Society Fall (AVS Fall 2017) Meeting
  • Clark et. al. AVS 2016 International Conference on Atomic Layer Deposition (ALD 2016)
  • Thibaut et. al. SPIE Advanced Lithography 2017
  • Mohanty et. al. SPIE Advanced Lithography 2017
  • Dey et. al. 2017 Conf. on Frontiers of Characterization and Metrology for Nanoelectronics (FCNM)
  • Clark et al. MRS 2017 Spring Meeting
  • Leusink, G. 2017 Area Selective Deposition (ASD 2017) Workshop
  • Chew et. al. 2017 IEEE International Interconnect Technology Workshop (IITC) accepted
  • Sharma et. al. 2017 Symposium on VLSI Technology (VLSI 2017) accepted
  • Clark et. al. 2017 AVS Atomic Layer Etching (ALE 2017) Workshop accepted

References and Additional Information

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