[PPT] - Vicis: A Reliable Network for Unreliable Silicon Andrew DeOrio, PowerPoint Presentation

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Vicis: A Reliable Network for Unreliable Silicon

Andrew DeOrio, David Fick, Jin Hu, Valeria Bertacco, David Blaauw, Dennis Sylvester

Electrical Engineering & Computer Science Department The University of Michigan, Ann Arbor

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Growing design complexity  modular architectures
Network-on-Chip (NoC)
Components (processors, memory, etc.) communicate via routers
Scalable bandwidth, inherent redundancy

Network-on-Chip

processor

router

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Technology-scaling increases likelihood of wear-out
Reasons include: oxide breakdown, electromigration, etc.

Transistor Wear-Out

The Bathtub Curve

Wearout Fault Rate Chip Time eliminated by burn-in eliminated by margining Useful Chip Lifetime

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Technology-scaling increases likelihood of wear-out
Reasons include: oxide breakdown, electromigration, etc.

Transistor Wear-Out

The Bathtub Curve

Wearout Fault Rate Chip Time Useful Chip Lifetime

Technology-scaling  shorter useful life

eliminated by burn-in eliminated by margining

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Technology-scaling increases likelihood of wear-out
Reasons include: oxide breakdown, electromigration, etc.

Transistor Wear-Out

The Bathtub Curve

Wearout Fault Rate Chip Time Useful Chip Lifetime Reclaimed by Vicis eliminated by burn-in eliminated by margining

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Vicis

System Response to Wear-Out

Errors Performance

No Protection

Detection Detect if fault has occurred Diagnosis Diagnose what fault has occurred Recovery Recover and resume normal operation

Checkpointing Invariants

Failure at first fault

Errors Performance

Triple Modular Redundancy

Failure after several faults

Errors Performance

Vicis

Graceful performance degradation

Reconfigure network to account for fault Reconfiguration

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Fault Tolerance Strategy

routing table crossbar input

utput

decoder

If faults are isolated, fault-free lanes may continue to operate

FIFO

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Outline

Architecture Overview
Diagnostic Approach
Experimental Results
Conclusion

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Network Assumptions

Wormhole routing
2D mesh or torus
Static routing
No virtual channels
Hard fault injection

W N E local

dest i packet flits ...

router i S

dest dir N 1 S n-1 W i local routing table

...

head data tail

. . .

...

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Vicis Reliability Features

routing table crossbar input

utput

decoder

FIFO

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Vicis Reliability Features

routing table crossbar input

utput

decoder ECC

FIFO

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Vicis Reliability Features

routing table crossbar bypass bus input

utput

decoder controller ECC

FIFO

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routing table crossbar bypass bus input

utput

decoder controller ECC

Vicis Reliability Features

port swapper

FIFO

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routing table crossbar bypass bus input

utput

decoder controller ECC

Vicis Reliability Features

BIST Controller

FIFO

port swapper

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routing table crossbar bypass bus input

utput

decoder controller ECC BIST Controller

FIFO

port swapper

Vicis Reliability Features

config. table

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routing table crossbar bypass bus input

utput

decoder controller ECC BIST Controller

FIFO

port swapper

config. table

Vicis Reliability Features

Distributed Algorithm Engine

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Input Port Swapping

Input ports decoder port swapper

Local North West South East

Partial crossbar gives

multiple connection

ptions
Priority given to local

port in order to increase # of available IPs

FIFO

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Input Port Swapping

R R R

X

R R

X

R R R

X

R R

X

Two Functional Links Three Functional Links Input Port Swap Input Port Output Port

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Bypass Bus

crossbar bypass bus controller

Provides alternative

path around crossbar

Round-robin arbiter

inside controller

No penalty for single

user, additional users must stall until free

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Error Correction Codes

BIST swap BIST

ECC/DEC ECC/DEC Link ECC-to-ECC Path

XB

bbus

XB

bbus

Six available paths between two routers
Only one fault may be corrected by ECC
Fault information for five unit types must be considered:
Crossbar, bypass bus, network link, input port swapper, FIFOs
All configurations must be performed simultaneously
Configurations affect each another, network wide

FIFO

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Error Correction Codes

BIST swap BIST

ECC/DEC ECC/DEC Link ECC-to-ECC Path

XB

bbus

XB

bbus

Single Bit Fault FIFO

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Network Re-routing [DATE 2009]

Distributed routing algorithm
Can route around an arbitrary

number of faulty links

Requires no virtual channels
Implemented in fewer than 300 gates

Destination Routed ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! !

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Hard Fault Diagnosis

Unit 1 Unit 2 Built-in-Self-Test

1 Stuck-0

Unit 1 Unit 2 Built-in-Self-Test

missed faults!

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Hard Fault Diagnosis

Pattern Based Testing

Error unit, crossbar controller, routing table,

decode/ECC, output ports, FIFO control

Datapath Testing

FIFO datapath, input port swapper, links,

crossbar, bypass bus, configuration table

LFSR

=

expected signature

to configuration table pre-recorded test bit flip counter save for reconfiguration routine

unit under test unit under test

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Experimental Setup

3x3 Torus
32-bit data flits, 32 flit buffers
Implemented in Verilog
Synthesized, automatic place and route in 45nm
Reliability results
Implemented in C++
Performance results
Injected stuck-at faults on gate outputs
Weighting based on gate area
10,000 packets per test, random uniform traffic
Parallel packet injection

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Results – Router Reliability

Key advantage: keep processors connected to network

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Results – Network Performance

20 40 60 80 100

Network Faults

1 2 3 4 5 6 7 8 9

Available Routers

~50% of routers work despite 100 faults ~1/2000 gates broken

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Results – Network Performance

20 40 60 80 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Network Performance

Normalized Network Throughput

Network Faults

1 2 3 4 5 6 7 8 9

Available Routers

throughput decreases as routers reconfigure throughput increases as network shrinks

5th-95th percentile

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Results – Network Reliability

10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100

TMR Vicis

Likelihood of Correct Operation (%)

Network Faults

Key Advantage: Extended MTTF 42% area overhead 200+% area overhead Key Advantage: Low area

verhead

*BulletProof: A Defect-tolerant CMP Switch Architecture, Constantinides, et al. 2006

different TMR granularities *

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Conclusion

Vicis can tolerate a large number of faults
Vicis provides much greater reliability than NMR based

solutions

Vicis: constant-reliability, probabilistic performance
NMR: constant-performance, probabilistic reliability
Vicis has an overhead of 42% versus 100+% for NMR