The QIE10/11 Elliot Hughes TIPP 2014: 140604 LPC Residents And - - PowerPoint PPT Presentation

The QIE10/11 (140604) Elliot Hughes Rutgers University 1

A New Generation Of Charge Integrating ADC For The CMS HCAL Upgrade:

The QIE10/11

Elliot Hughes

TIPP 2014: 140604 LPC Residents And Visitors:

• J. Chou1, H. Hernandez2, E. Hughes1, T. Roy2, F. Yumiceva2

1Rutgers University, 2Florida Institute Of Technology (FIT)

Fermilab Physicists:

• J. Freeman, D. Hare, J. Hirschauer, A. Whitbeck, J. Whitmore

Fermilab Engineers And Technicians:

• A. Baumbaugh, L. Dal Monte, T. Shaw, T. Zimmerman

About This Presentation

Presentation Outline:

(0) Context (1) The QIE10/11 (2) Single-Chip Tests (3) ADC Response (4) TDC Response (5) Other Tests (6) Radiation Tolerance (7) Conclusion

Teststand at Fermilab

The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 2 Simple English Summary:

The QIE is an electronic chip that takes a current signal and integrates it over 25 nanosecond periods. The CMS hadron calorimeter (HCAL) uses these chips to measure energy. This presentation is about the testing and verifjcation of the QIE, which takes place at Fermilab.

The QIE10 Tests (140507) Elliot Hughes Rutgers University 2 The QIE10/11 (140604) Elliot Hughes Rutgers University 2

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 3 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 3 The QIE10 Tests (140507) Elliot Hughes Rutgers University 3

(0) The CMS Detector

Forward Hadron Calorimeter (HF): Important for measuring forward jets and luminosity Hadron Calorimeter Barrel (HB) And Endcaps (HE): Measures the energy of hadrons and, indirectly, the energy of non-interacting particles such as neutrinos

Before I talk about the chip, let me motivate it by putting it in the context of the compact muon solenoid (CMS) detector:

(0) The QIE

The QIE chip is the analog-to-digital (ADC) application-specifjc integrated circuit (ASIC) that digitizes data from the hadron calorimeter (HCAL) photodetectors:

The QIE10/11 (140604) Elliot Hughes Rutgers University 4

(1) QIE Overview

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 5 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 5 The QIE10 Tests (140507) Elliot Hughes Rutgers University 5

History:

• 1989: Invented by Bill Foster for the Solenoid Detector

Collaboration (SDC) at the Superconducting Super Collider (SSC)

• 1995 (QIE5): First functioning prototype designed by Thomas

Zimmerman for the Kaons At The Tevatron (KTeV) experiment at Fermilab

• 1996 (QIE6): Used in the calorimetry of the Collider Detector

At Fermilab (CDF)

• 2002 (QIE7): Used in the front-end of the Main Injector

Neutrino Oscillation Search (MINOS) Near Detector at Fermilab

• 2003 (QIE8): Used in the front-end of the CMS HCAL at CERN
• 2014 (QIE10/11): New versions designed for the CMS HCAL

Phase 1 Upgrade

QIEx:

(Q) Charge ( I ) Integrator and (E ) Encoder ( x ) version #

The diameter of a US penny is 3/4 in, or ~ 2 cm The QIE10/11 (140604) Elliot Hughes Rutgers University 5

(1) QIE10/11 Design

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 6 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 6 The QIE10 Tests (140507) Elliot Hughes Rutgers University 6

Features:

• Deadtimeless operation at 40 MHz (25 ns): Achieved by four-phase operation (see next slide)
• Large dynamic range: About 400 fC at about 3 fC resolution, this is 10 times wider than the

previous version.

• Timing information (TDC): The position in time of the fjrst rising edge is measured with 500 ps

resolution.

• Programmable: Pedestal, timing threshold, and operation mode settings are all confjgurable.
• Internal calibration: An eight-valued charge injector inside the chip can be used for rudimentary

calibration.

• Low power draw: The chip draws about 310 mW.
• 350 nm AMS SiGe fabrication process: This is the fjrst QIE version designed with this process.
• Programmable gain (QIE11): The QIE11 features a programmable gain by providing a

confjgurable series of current shunts at the input.

The QIE10 and the QIE11 are identical in design, except the QIE11 includes a programmable current shunt:

The QIE10/11 (140604) Elliot Hughes Rutgers University 6

(1) QIE10/11 Design

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 7 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 7 The QIE10 Tests (140507) Elliot Hughes Rutgers University 7 The QIE10/11 (140604) Elliot Hughes Rutgers University 7

Deadtimelessness is achieved by four operational phases:

• Integrate, range select, digitize, reset

integrator

• Each phase takes 25 ns, so four pipelines are

run in parallel.

• Each pipeline is identifjed by a capacitor ID

(CapID).

(2) Single-Chip Tests

The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 8 The QIE10 Tests (140507) Elliot Hughes Rutgers University 8

Summary of single-chip tests

Test Chips Success Operable 310 299/310 (96 %) Dynamic Range: (A) ranges present 20 20/20 (100 %) Dynamic Range: (B) charge 20 20/20 (100 %) Range Overlap 299 296/299 (99 %) 100 98/100 (98 %) 100 99/100 (99 %) Pedestals: (C) tuned 100 100/100 (100 %) Pedestals: (D) tuned spread 100 100/100 (100 %) Pedestals: (E) pedestal DAC 100 99/100 (99 %) ADC: (A) nominal bin widths 20 20/20 (100 %) ADC: (B) DNL 20 20/20 (100 %) ADC: (C) coarse bin widths 299 288/299 (96 %) TDC: (A) detailed 1 1/1 (100 %) TDC: (B) coarse 20 20/20 (100 %) TDC: (C) special codes 299 299/299 (100 %) Pulse Integration 1 1/1 (100 %) Stability 1 1/1 (100 %) QIE11 Shunts 1 1/1 (100 %) Total Yield 310 281/310 (91 %) Pedestals: (A) untuned Pedestals: (B) untuned spread We have 310 packaged QIE10 chips and 20 QIE11 chips that we study.

• With this amount of chips

we're able to get a hint of large batch performance and yields.

• Tests are performed at

Fermi National Accelerator Laboratory (Fermilab) in Illinois, USA.

• “Chips”: number of

chips used in specifjc test

• “Success”: number

(percentage) of chips that passed the test's specifjcations for acceptable performance The QIE10/11 (140604) Elliot Hughes Rutgers University 8

(3) ADC Response

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 9 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 9 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 9 The QIE10 Tests (140507) Elliot Hughes Rutgers University 9

The following sketch illustrates how the ADC functionality works:

The QIE10/11 (140604) Elliot Hughes Rutgers University 9

(3) ADC: Dynamic Range

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 10 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 10 ADC Count Ve Versus Input Charge

ADC Code Input Charge (fC)

The dynamic range of the QIE10 is roughly 400 pC. This is a plot showing the entire dynamic range of a chip:

The QIE10 Tests (140507) Elliot Hughes Rutgers University 10 The QIE10/11 (140604) Elliot Hughes Rutgers University 10

(3) ADC: Subranges

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 11 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 11

Each of the 4 ranges are divided into 4 subranges. Each subrange has a difgerent characteristic bin width:

Range 1 Mantissa Versus Input Charge

ADC Code (Range 1) Input Charge (fC)

The QIE10 Tests (140507) Elliot Hughes Rutgers University 11 The QIE10/11 (140604) Elliot Hughes Rutgers University 11

(3) ADC: Subranges

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 12 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 12

2 3 4 10 20 30 40 50 4 6 8 10 20 30 40 50 60 70 8 10 12 14 16 18 20 40 60 80 15 20 25 30 35 10 20 30 40 50 60 70

Range 0 Bin Widths

Subrange 0 Chips Average Bin Width (fC) Subrange 1 Subrange 2 Subrange 3 Chips Chips Chips Average Bin Width (fC) Average Bin Width (fC) Average Bin Width (fC)

For 80 chips, we measure each subrange's bin width:

We don't expect measured bin widths to be exactly equal to the nominal values. Between chip production runs, bin widths will difg fger on the order of 10 % due to normal and expected process variations.

The QIE10 Tests (140507) Elliot Hughes Rutgers University 12 The QIE10/11 (140604) Elliot Hughes Rutgers University 12

(3) ADC: Subranges

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 13 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 13 The QIE10 Tests (140507) Elliot Hughes Rutgers University 13

• 2
• 1

1 2

200 400 600 800 1000

• 2
• 1

1 2

500 1000 1500

• 2
• 1

1 2

500 1000 1500

• 2
• 1

1 2

100 200 300 400

Difg fgerential Nonlinearity Per Subrange

Subrange 0 ADC Bins DNL DNL DNL DNL Subrange 1 Subrange 2 Subrange 3 ADC Bins ADC Bins ADC Bins

We want the bin widths to have the correct average value, but we also want the bins to be consistent within each subrange:

The QIE10/11 (140604) Elliot Hughes Rutgers University 13

(3) ADC: Range Overlap

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 14 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 14

Input Charge (fC) ADC Code

Overlap Between Range 0 And Range 1

Mean 3.111 Underflow Overflow 1

1 2 3 4 5 6 50 100 150 200 250

Mean 3.111 Underflow Overflow 1

Overlap Between Ranges 0 and 1

Chips Overlap (ADC Code)

For 299 chips, we measure each range overlap: The bins at the intersections between ranges are intentionally constructed to

• verlap. This prevents gaps between ranges, which would result in loss of signal.

The bin width is the same for bins in the highest subrange of a specifjc range and the lowest subrange in the next range.

The QIE10 Tests (140507) Elliot Hughes Rutgers University 14 The QIE10/11 (140604) Elliot Hughes Rutgers University 14

(4) TDC Response

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 15 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 15 The QIE10 Tests (140507) Elliot Hughes Rutgers University 15

The following sketch illustrates how the TDC functionality works:

The QIE10/11 (140604) Elliot Hughes Rutgers University 15

(4) TDC: Bin Architecture

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 16 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 16

5 10 15 20 25 10 20 30 40 50

TDC Code Pulse Delay (ns) TDC Code Versus Pulse Delay

Mean 0.002 Underflow Overflow

• 1
• 0.5

0.5 1 5 10 15 Mean 0.002 Underflow Overflow

TDC Difg fgerential Nonlinearity (DNL) TDC Bins DNL

Since TDC functionality is a new feature to the QIE, our original teststand is not ideally suited to studying TDC response. Each chip we look at in detail must be soldered to a modifjed testboard.

These plots show the TDC response of a chip:

The QIE10 Tests (140507) Elliot Hughes Rutgers University 16 The QIE10/11 (140604) Elliot Hughes Rutgers University 16

(4) TDC: Special Codes

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 17 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 17 The QIE10 Tests (140507) Elliot Hughes Rutgers University 17

For each chip, we set two difgerent TDC thresholds and inject charge at points well below and well above this threshold.

61 62 63 100 200 300 61 62 63 100 200 300

Below Threshold Above Threshold

Chips Chips TDC Code TDC Code

Special Codes: 61: Delay lock loop unlocked. This is bad;

it means the TDC won't function correctly.

62: Input current stayed above threshold

for the whole integration window.

63: Input current stayed below threshold

for the whole integration window.

The QIE10/11 (140604) Elliot Hughes Rutgers University 17

(5) Pulse Integration

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 18 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 18 The QIE10 Tests (140507) Elliot Hughes Rutgers University 18

Measured Charge Versus Pulse Delay, Per Integration Window Measured Charge (fC) Pulse Delay (ns)

It's crucial that a pulse is integrated to the same total charge regardless of its position in time. In the following study, we slowly delay a pulse across a number

• f integration windows and fjnd the total charge at each time:

The QIE10/11 (140604) Elliot Hughes Rutgers University 18

(5) Programmable Gain

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 19 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 19 The QIE10 Tests (140507) Elliot Hughes Rutgers University 19 The QIE10/11 (140604) Elliot Hughes Rutgers University 19

ADC Code Versus Input Charge For Difg fgerent Shunt Settings x12

There are 12 identical current shunts at the input of the QIE11. Together, they form a 12-valued programmable gain for the input signal. Here are the ADC response curves of fjve difgerent shunt settings, for a representative chip:

(6) Radiation Tests

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 20 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 20 The QIE10 Tests (140507) Elliot Hughes Rutgers University 20 The QIE10/11 (140604) Elliot Hughes Rutgers University 20

The QIE10/11 is more radiation tolerant than previous versions:

• The chip performs acceptably up to

and past target specifjcations of 10 krad total ionizing dose (TID) and 2x1012 neutrons/cm2 of fmuence.

• No errors were seen in parts of the

chip designed to be radiation hard (the shadow register).

(7) Conclusion

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 21 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 21 The QIE10 Tests (140507) Elliot Hughes Rutgers University 21 The QIE10/11 (140604) Elliot Hughes Rutgers University 21

• Bench tests conducted at

Fermilab have successfully validated the performance of the QIE10/11.

• The QIE10/11 design is

complete and ready for the CMS HCAL Phase 1 Upgrade.

• The QIE10 might be used in
• ther experiments: A Toroidal

LHC Aparatus (ATLAS) and the CMS Beam Halo Monitor (BHM). Add your experiment to the list!

Teststand at Fermilab

(-1) Extra

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 22 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 22 Quantization Error Versus Input Charge

Input Charge (pC) Quantization Error

The QIE10 Tests (140507) Elliot Hughes Rutgers University 22

Why difgerent bin sizes are necessary:

The QIE10/11 (140604) Elliot Hughes Rutgers University 22

(-1) Extra

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 23 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 23 The QIE10 Tests (140507) Elliot Hughes Rutgers University 23

How to coarsely measure bin widths:

Input Charge (fC) ADC Count (Range 1) Input Charge Versus ADC Count, Range 1 The QIE10/11 (140604) Elliot Hughes Rutgers University 23

(-1) Extra

The Performance Of The QIE10 Prototype 5 (140321) Elliot Hughes Rutgers University 24 The QIE10 Prototype 5 Tests (140507) Elliot Hughes Rutgers University 24 The QIE10 Tests (140507) Elliot Hughes Rutgers University 24

This is how we measure the range overlap:

The QIE10/11 (140604) Elliot Hughes Rutgers University 24