The Design Complexity of Program Undo Support in a General - - PowerPoint PPT Presentation

The Design Complexity of Program Undo Support in a General Purpose Processor

Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Speculative execution over large code

sections Rollback/re-play of program execution Very low overhead Speculation exposed to the software

Safe Code Begin Spec Safe Code End Spec

Processor with program undo support

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Safe Code Safe Code Speculative code Begin Spec End Spec End Spec

Safe Speculative

Some Code

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Applications of program undo

Safety net for speculating over: correctness of aggressive optimizations:

thread level speculation, value prediction, speculative synchronization

system reliability:

software - primitive for software debugging

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• How complex is

program undo support?

Determined the hardware needed Implemented it in a simple processor Prototyped it using FPGA technology Estimated complexity using three metrics: Hardware overhead, development time, VHDL code size

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Implementation of

program undo support

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CPU RF CKPT Data Cache

Save/restore processor state, buffer speculative data, control transitions:

Memory

• 1. Register checkpointing and

restoration

• 2. Data cache that buffers

speculative data

• 3. Instructions enable/disable

speculation on-the-fly

Safe Speculative

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Register checkpointing

Beginning of the speculative section RF saved into a Shadow RF PC, state registers are saved End of speculative section Commit: discard checkpoint Rollback: restore RF & PC

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IDLE CHECKPOINT ROLLBACK RESTORE

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Data cache extensions

Holds both speculative and non- speculative data Speculative lines will not be evicted to memory Cache walk state machine: Commit: merge lines Rollback: invalidate speculative lines

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Data Cache

1 1

Memory

IDLE WALK RESTORE

Safe Speculative

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Software control

Give the compiler control over speculative execution Added control instructions: Begin speculation End speculation (commit or rollback) We use SPARC’s special access load

LDA [r0] code, r1

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Hardware prototype

LEON2 - SPARC V8 compliant processor In-order, single issue, 5-stage pipeline Windowed register file L1 instruction and data caches Synthesizable, open source VHDL code Fully functional, runs Linux embedded

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• System deployment

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Processor Image Control App. I/O Terminal Binaries PCI

C O M J T A G

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Evaluating design complexity

Hardware overhead, development time, VHDL code size Major components: register checkpointing speculative cache software control Comparison: write-back cache controller

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Hardware overhead

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• Avg. 4.5% overhead

1000 2000 3000 4000 5000 6000 7000 8000 9000 4KB 8KB 16KB 32KB 64KB

Data cache size CLBs software control speculative cache register checkpointing write back extensions baseline processor

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Development time

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100 200 300 400 500 600 700 800 900

WB Cache Controller Speculative Cache Register Checkpointing Software Control

Time (man-hours) Testing Implementation Design

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Lines of code

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500 1000 1500 2000 2500 3000 3500 Data Cache Controller Pipeline

Lines of VHDL code

Software control Speculative cache Register checkpointing Write back extensions Baseline unit

14.5% 7.5%

Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Conclusions

Program undo support is reasonably easy to implement Complexity similar to adding write-back support to a write-through cache controller Qualifying factor: Relatively simple processor

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Radu Teodorescu - University of Illinois Design Complexity of Program Undo

• Thank you!

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Short demo and questions...