������� ����� The Design Complexity of Program Undo Support in a General Purpose Processor Radu Teodorescu and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu
������� ����� Processor with Safe program undo support Speculative Safe Code Safe Code Speculative execution over large code sections Begin Spec Begin Spec Rollback/re-play of program execution Speculative code Some Code Very low overhead End Spec End Spec End Spec Speculation exposed to the software Safe Code Safe Code Radu Teodorescu - University of Illinois 2 Design Complexity of Program Undo
������� ����� Applications of program undo Safety net for speculating over: correctness of aggressive optimizations: thread level speculation, value prediction, speculative synchronization system reliability: software - primitive for software debugging Radu Teodorescu - University of Illinois 3 Design Complexity of Program Undo
������� ����� How complex is program undo support? Determined the hardware needed Implemented it in a simple processor Prototyped it using FPGA technology Estimated complexity using three metrics: Hardware overhead, development time, VHDL code size Radu Teodorescu - University of Illinois 4 Design Complexity of Program Undo
������� ����� Implementation of Safe program undo support Speculative Save/restore processor state, CKPT RF buffer speculative data, control transitions: CPU 1. Register checkpointing and restoration 2. Data cache that buffers Data Cache speculative data 3. Instructions enable/disable speculation on-the-fly Memory Radu Teodorescu - University of Illinois 5 Design Complexity of Program Undo
������� ����� Register checkpointing Beginning of the speculative section RF saved into a Shadow RF PC, state registers are saved IDLE End of speculative section CHECKPOINT ROLLBACK RESTORE Commit: discard checkpoint Rollback: restore RF & PC Radu Teodorescu - University of Illinois 6 Design Complexity of Program Undo
������� ����� Data cache extensions Safe Speculative Holds both speculative and non- 0 1 speculative data 0 1 Data Cache Speculative lines will not be evicted to memory Cache walk state machine: Memory Commit: merge lines IDLE Rollback: invalidate speculative WALK RESTORE lines Radu Teodorescu - University of Illinois 7 Design Complexity of Program Undo
������� ����� Software control Give the compiler control over speculative execution Added control instructions: Begin speculation End speculation (commit or rollback) We use SPARC’s special access load LDA [r0] code, r1 Radu Teodorescu - University of Illinois 8 Design Complexity of Program Undo
������� ����� Hardware prototype LEON2 - SPARC V8 compliant processor In-order, single issue, 5-stage pipeline Windowed register file L1 instruction and data caches Synthesizable, open source VHDL code Fully functional, runs Linux embedded Radu Teodorescu - University of Illinois 9 Design Complexity of Program Undo
������� ����� System deployment J T A Processor G Image C O M PCI I/O Terminal Binaries Control App. 10 Radu Teodorescu - University of Illinois Design Complexity of Program Undo
������� ����� Evaluating design complexity Hardware overhead, development time, VHDL code size Major components: register checkpointing speculative cache software control Comparison: write-back cache controller Radu Teodorescu - University of Illinois 11 Design Complexity of Program Undo
������� ����� Hardware overhead 9000 8000 Avg. 4.5% overhead 7000 software control 6000 speculative cache 5000 CLBs register 4000 checkpointing write back 3000 extensions baseline 2000 processor 1000 0 4KB 8KB 16KB 32KB 64KB Data cache size Radu Teodorescu - University of Illinois 12 Design Complexity of Program Undo
������� ����� Development time 900 800 700 Time (man-hours) 600 Testing 500 Implementation 400 300 Design 200 100 0 WB Cache Speculative Register Software Controller Cache Checkpointing Control Radu Teodorescu - University of Illinois 13 Design Complexity of Program Undo
������� ����� Lines of code 3500 7.5% 3000 2500 Lines of VHDL code Software control 2000 Speculative cache 14.5% Register checkpointing 1500 Write back extensions Baseline unit 1000 500 0 Data Cache Pipeline Controller Radu Teodorescu - University of Illinois 14 Design Complexity of Program Undo
������� ����� Conclusions Program undo support is reasonably easy to implement Complexity similar to adding write-back support to a write-through cache controller Qualifying factor: Relatively simple processor Radu Teodorescu - University of Illinois 15 Design Complexity of Program Undo
������� ����� Thank you! Short demo and questions... Radu Teodorescu - University of Illinois 16 Design Complexity of Program Undo
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