Testing of the DHE Modules Dima Levit, Paolo Di Giglio Physik - - PowerPoint PPT Presentation
Testing of the DHE Modules Dima Levit, Paolo Di Giglio Physik Department E18 - Technische Universitt Mnchen The 19th International Workshop on DEPFET Detectors and Applications May 12nd, 2015. Kloster Seeon supported by:
Dima Levit, Paolo Di Giglio
Physik Department E18 - Technische Universität München
The 19th International Workshop on DEPFET Detectors and Applications May 12nd, 2015. Kloster Seeon
supported by: Maier-Leibnitz-Labor der TU und LMU München, Cluster of Excellence: Origin and Structure of the Universe, BMBF
Belle
Tests at CAD-UL Tests at TUM
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 2/16
Tests at CAD-UL Tests at TUM
Tests at CAD-UL Tests at TUM High Speed Links Current Source
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 3/16
Tests at CAD-UL Tests at TUM
52 (Belle II) and 18 (Photon Factory) DHE/DHC modules v.3.2 are produced and are tested by the board manufacturer (CAD-UL GmbH). Tests started on the January 28th.
4x1.52 Gb/s
...
15x6.25 Gb/s
Unit under Test PC
Ethernet/IPBus
DHP Data Generator
Ethernet/IPBus
High Speed Data Generator
DDR3 Flash Clock Synthesizer
Hardware Setup Carrier board Hameg 4040 four channel power supply A nettop PC with test software
Low FPGA core voltage (0.5 V instead of 1 V)
wrong feedback resistance for DC/DC converter
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 4/16
Tests at CAD-UL Tests at TUM
Test environment based on python scripts and standard DHH programs
mostly automated, power supplies controlled by the script results stored in log files and paper check lists implemented return values in clock synthesizer and flash programmer:
return != 0 - fail should be used in PXD slow control state machines
Time for test: 5 min / module Tested items:
IPBus Ethernet link: used for configuration and reading test results. OK. Flash programming: return value of the program, revision check. OK. Clock synthesizer: return value of the program. OK. DDR3 memory: test core with error counter. 0 errors. Power consumption: OK.
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 5/16
Tests at CAD-UL Tests at TUM
Tests at CAD-UL Tests at TUM High Speed Links Current Source
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 6/16
Tests at CAD-UL Tests at TUM
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 7/16
Tests at CAD-UL Tests at TUM
4 DHP high speed links: 1.52 Gb/s aurora with error counter and signal eye amplitude, BER up to 6.8·10−13 Current source: coarse test with resistive load (10.1 kOhm) installed on adapter board
One module has link established, while eyeamplitude stays at 0
DFEEYEAMPLITUDE is not a good parameter to monitor
Unstable aurora channels on some cards
Test repeated with IBERT (Internal Bit-Error Rate) core
Current source problems: offset current varies between cards
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 8/16
Tests at CAD-UL Tests at TUM
10 minutes test with IBERT, same parameters as with aurora links Worst case link: 500 errors Problem identified:
automatic calibration of the decision feedback equalizer (DFE) Xilinx recommends to switch DFE calibration to the manual mode for 8b/10b signal (Answer Record #45483)
New tests without automatic DFE calibration: all channels OK
previous link with 500 errors: 0 errors over 4 days (BER < 2·10−15)
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 9/16
Tests at CAD-UL Tests at TUM
DAC 10000 20000 30000 40000 50000 60000 70000 ADC 500 1000 1500 2000 2500 3000 3500 4000
ADC:DAC, Module 0021
DAC 10000 20000 30000 40000 50000 60000 70000 ADC 500 1000 1500 2000 2500 3000 3500 4000
ADC:DAC, Module 0062
Offset current differs from module to module
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 10/16
Tests at CAD-UL Tests at TUM
DHP_SENSE_VCC NC 1 VIN 2 NC 3 GND 4 NC 5 VOUT 6 NC 7 TP 8 U25 ADR4525BRZ GND DACVref C266 2.2uF GND +5V GND DACout DIN 1 VDD 2 VREF 3 VOUT 4 AGND 5 DACGND 6 SYNC 7 SCLK 8 U26 ADI-AD5060-RJ-8 DCD_SCK DCD_SDI DCD_CS0 VREF 1 IN+ 2 IN- 3 VSS 4 CS/SHDN 5 DOUT 6 CLK 7 VDD 8 U24 MCP3201 GND GND R167 ADCin DNI R168 GND C268 100n 3 4 5 1 6 7 2 U27 AD8276 GND GND GND VtoI OA2out Vout VloadSense GND R177 GND 10k 0.05%, 0805, ± 10ppm/°C R169 ERA6ARW103P 2.2 R178 D14 PMEG2500CT DCD_CURMON_P 3 1 8 2 5 4 7 6 U28 AD8607AR (SOIC) DCD_CS0 DCD_CS1 DCD_SDO DCD_SDI DCD_SCK DCD_MON DCD_MON +5V GND +2.7V GND +5V +5V R170 0 C275 100nF C274 100nF C269 100nF C267 100nF C265 100nF
High reverse current at protection diode Problem fixed by replacing the component with the diode with lower reverse current
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 11/16
Tests at CAD-UL Tests at TUM
Offset Current, uA 15 20 25 30 35 Gain, nA/DAC 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3.95 4
Offset Current vs Gain
Figure : Gain fit with old diodes
Offset Current, uA 0.8 − 0.6 − 0.4 − 0.2 − 0.2 Gain, nA/DAC 3.815 3.82 3.825 3.83 3.835
Offset Current vs Gain
Figure : Gain fit with new diodes
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 12/16
Tests at CAD-UL Tests at TUM
Offset Current, uA 15 20 25 30 35 Gain, nA/DAC 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3.95 4
Offset Current vs Gain
Figure : Gain fit with old diodes
Offset Current, uA 0.8 − 0.6 − 0.4 − 0.2 − 0.2 Gain, nA/DAC 3.815 3.82 3.825 3.83 3.835
Offset Current vs Gain
Figure : Gain fit with new diodes
Offset Current, uA 5 10 15 20 25 30 35 40 Gain, nA/DAC 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3.95 4
Offset Current vs Gain
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 12/16
Tests at CAD-UL Tests at TUM
Full test and characterization of the 52 DHE modules (Belle 2): all good Basic test of the 18 DHE modules(Photon Factory) at CAD-UL: all good Variable offset current on current sources solved by replacing protection diode with lower reverse current Problem with DFE on the DHPT high speed links found. No problems caused by hardware.
Next firmware update will address this issue.
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 13/16
Tests at CAD-UL Tests at TUM
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 14/16
Tests at CAD-UL Tests at TUM
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 15/16
Tests at CAD-UL Tests at TUM
Outer Forward Outer Backward
DCD1 DCD2 DCD3 DCD4 DHP1 DHP2 DHP3 DHP4
Dima Levit, Paolo Di Giglio | Testing of the DHE Modules 16/16