System Design of a Digital High-Speed Modular Satellite Downlink - - PowerPoint PPT Presentation

system design of a digital high speed modular satellite
SMART_READER_LITE
LIVE PREVIEW

System Design of a Digital High-Speed Modular Satellite Downlink - - PowerPoint PPT Presentation

System Design of a Digital High-Speed Modular Satellite Downlink Sren F. Peik Inst. of Aerospace Technology Bremen Outline Motivation Design for Space The DATARAIN System Conclusions Motivation Satellite for Scientific Missions Mass


slide-1
SLIDE 1

System Design of a Digital High-Speed Modular Satellite Downlink

Sören F. Peik

  • Inst. of Aerospace Technology Bremen
slide-2
SLIDE 2

Outline

The DATARAIN System Conclusions Design for Space Motivation

slide-3
SLIDE 3

Motivation

slide-4
SLIDE 4
slide-5
SLIDE 5

Satellite for Scientific Missions

Ground Station 1 Ground Station 2

Telemetry Instruments ~1 GBits/s Mass Storage ~1 TBit Downlink ~100Mbit/s

User Down Link Intersatellite Link Telemetry Link

slide-6
SLIDE 6

101101011 Ground Station

1000 MBit/s

slide-7
SLIDE 7

Design for Space

slide-8
SLIDE 8

Challenge 1: Space Environment

Vacuum Temperature Vibration Radiation

slide-9
SLIDE 9

Challenge 2: Bandwidth Efficiency

f [MHz] 8025 8400 CCSDS

DSN

slide-10
SLIDE 10

Challenge 3: Reliability

slide-11
SLIDE 11

Challenge 4: Doppler Shift

v

5 1 0 1 5 2 0 8 . 1 9 9 8 8 . 1 9 9 8 8 . 1 9 9 9 8 . 1 9 9 9 8 . 2 8 . 2 0 0 1 8 . 2 0 0 1 8 . 2 0 0 2 8 . 2 0 0 2

C e n t e r f r e q u e n c y o v e r t h e t r a n s m i s s i o n t i m e

t [ m i n u t e s ] f [ G H z ]

slide-12
SLIDE 12
  • CCSDS Compliant
  • Space Qualifiable Transmitter
  • Low Mass, Low Power System
  • X-Band System 8025-8040 MHz,

Options for other Bands

  • Achievable Rates using α=0.35 Roll-off:

Modulation Bit/Hz

  • max. Data Rate

QPSK 2 Bit/Hz 555,56 MBit/s 8 PSK 3 Bit/Hz 833,34 MBit/s 16 QAM 4 Bit/Hz 1111,12 MBit/s

Requirements:

slide-13
SLIDE 13

The System

slide-14
SLIDE 14

Transmitter Channel DATA IN Receiver DATA OUT

slide-15
SLIDE 15

Transmitter:

IF- Board RF- Frontend Antenna

8 GHz 1.4 GHz

Baseband Processor

slide-16
SLIDE 16

Blockdiagram

LO

IF-Filter Anti Aliasing Filter IQ-Mod.

DAC LO DAC FPGA

RF-Filter P.-Amp. Mixer Image rejection Filter

LO I n t e r f a c e P C Power Supply 3.3V 5V

Base Band Board IF-Board RF-Front-End X-Band RF-Front-End C-Band

12V

I Q

I n t e r f a c e

RF-Filter P.-Amp. Mixer Image rejection Filter

LO

slide-17
SLIDE 17

Baseband Processor

DAC LO DAC FPGA I n t e r f a c e P C

Base Band Board I Q

I n t e r f a c e

slide-18
SLIDE 18

Baseband Processor

Clock FPGA Power Supply I+ I- Q- Data Input Configuration Interface Q+ D/A Converter

slide-19
SLIDE 19
slide-20
SLIDE 20

Simulation versus Measurement

slide-21
SLIDE 21

16 APSK

slide-22
SLIDE 22

IF Board

LO

IF-Filter Anti Aliasing Filter IQ-Mod.

IF-Board I Q

slide-23
SLIDE 23
slide-24
SLIDE 24
slide-25
SLIDE 25

RF Front End

RF-Filter P.-Amp. Mixer Image rejection Filter

LO

RF-Front-End X-Band

slide-26
SLIDE 26
slide-27
SLIDE 27

RF Spectrum

slide-28
SLIDE 28

Receiver ADC and FPGA IQ-Demodulator LP-Filter LP-Filter

  • Freq. Generator

BP-Filter Mixer AGC

  • Freq. Generator

LN-Amp. DATA Mixer BP-Filter

  • Freq. Generator

BP-Filter

Receiver

slide-29
SLIDE 29

Conclusions

  • Space Calls for a Deliberate Design
  • High Speed Links are a Challenge for

Digital and Analog System Sections

  • We still Need Analog Design

(Electromagnetic Waves are Analog)

  • Interaction of Digital and Analog Sections is

a Must

slide-30
SLIDE 30

Thank You