Synthesis Engine Cus T f pla an i Mohamed El-Hadedy *+ , Xinfei - - PowerPoint PPT Presentation

synthesis engine
SMART_READER_LITE
LIVE PREVIEW

Synthesis Engine Cus T f pla an i Mohamed El-Hadedy *+ , Xinfei - - PowerPoint PPT Presentation

P This poster is 48 wide by 36 high. Its designed to be printed on a RE-HASE: Regular-Expressions Hardware l Synthesis Engine Cus T f pla an i Mohamed El-Hadedy *+ , Xinfei Guo + + , Xiaoping Huang ^^, Martin Margala ** SmartA


slide-1
SLIDE 1

P

This poster is 48” wide by 36” high. It’s designed to be printed on a l

Cus

T f pla an i SmartA multi T f bu If titl mak drag it into place. PowerPoint’s Smart w W i righ C pr b

Mohamed El-Hadedy*+, Xinfei Guo + +, Xiaoping Huang ^^, Martin Margala**

+Department of Computer Science, University of Virginia, Charlottesville, Virginia, USA + + Department of Electrical and Computer Engineering, University of Virginia, Virginia, USA *Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, Illinois, USA ** Department of Electrical and Computer Engineering, University of Massachusetts Lowell, MA, USA

^^Department of Electrical and Computer Engineering , Northwestern Polytechnic University, China

RE-HASE: Regular-Expressions Hardware Synthesis Engine

Email: hadedy@Illinois.edu, mea4c@virgina.edu

slide-2
SLIDE 2

What is a Regular Expression?

  • A regular expression (regex) describes a pattern to match multiple input

strings.

  • Regular expressions descend from a fundamental concept in Computer

Science called finite automata theory

  • Regular expressions are endemic to Unix
  • Some utilities/programs that use them:

–vi, ed, sed, and emacs –awk, tcl, perl and Python –grep, egrep, fgrep –compilers

  • The simplest regular expression is a string of literal characters to match.
  • The string matches the regular expression if it contains the substring.
slide-3
SLIDE 3

What is a DFA and NFA?

An NFA is a Nondeterministic Finite Automaton. Nondeterministic means it can transition to, and be in, multiple states at once (i.e. for some given input). A DFA is a Deterministic Finite Automaton. Deterministic means that it can only be in, and transition to, one state at a time (i.e. for some given input).

slide-4
SLIDE 4

Code Automatically Generation

  • State Transition: Construct the state machine

transition

  • State

Condition: Extract the matching condition between different DFA states and drive the state to jump

  • Match

Report: Collect the matching information and output onto the bus

State Transitio n

State Condition Match Report Code Automatically Generation Regex Preprocess Brill Back-door Dot-star FPGA Tools Synthesis, Mapping, and Placement and routing DF A HDL

RE-HASE Tool

slide-5
SLIDE 5

FPGA internal Architecture: parallel matching

Report and Post-Process Symbol Streaming PCIE Bus Matching Streaming FIFO Controller Input FIFO Output FIFO

slide-6
SLIDE 6

Regrouping for shared Memory Architecture

Benchmark (1) Benchmark (2)

slide-7
SLIDE 7

FPGA Synthesis Results for Benchmarks with Xilinx-V7 VC707 Board

Benchmark Critical Path Delay (ns) Logic Latency (ns) Route Latency (ns) Utilization (%) dotstar005 1.257 0.256 1.001 2% dotstar010 1.269 0.26 1.009 2% dotstar020 1.294 0.269 1.025 2% Spyware_put 1.34 0.26 1.08 1.2% backdoor 1.42 0.25 1.17 3.5%

slide-8
SLIDE 8

Synthesis Results of Benchmarks on 28nm

Bench mark Critical Path Delay (ns) Static Power (mW) Dynamic Power (W) Total Power (W) Area (mm2) # of gates (K)

Dotstar0 05 0.16 0.9582 0.284 0.2851 0.08653 176.70 dotstar0 10 0.20 0.9612 0.285 0.2860 0.08680 177.30 dotstar0 20 0.17 0.9513 0.282 0.2829 0.08588 175.40 spyware _put 0.28 0.2807 0.082 0.0822 0.02533 51.70 backdoor 0.24 0.1883 0.083 0.0831 0.01651 33.70

slide-9
SLIDE 9

Conculsion

9
  • Python Tool (RE-HASE), which can transfer the NFA/DFA

to RTL.

  • Ability to direct the RTL to either ASIC/FPGA based on the

application

  • Novel features for better optimization regarding using

resources without decreasing the total performance

slide-10
SLIDE 10

Future Work

10
  • Using the regrouping feature with the coherency interfaces

such as CAPI (IBM), QPI (Intel) to improve the total performance of the RegEx Engine based on the RE-HASE

  • Using the ability of producing the same feature for using

small devices for the IoT applications

  • Integrating RE-HASE to HLS applications as a library
slide-11
SLIDE 11

Current research

11
  • El-Hadedy, Mohamed; Guo, Xinfei; Hwu, Wen-Mei; Stan, Mircea; Skadron, Kevin. Crypt-Pi: A Light and Fast

Crypto-Processor for IoT Applications, TECHCON-2017, Austin, TX, September 20-22, 2017. (Best Paper Award)

  • El-Hadedy, Mohamed; Guo, Xinfei; Stan, Mircea; Skadron, Kevin ; Hwu, Wen-Mei. R-NNPE: Reconfigurable

Neural Network Processing Elements, TECHCON-2017, Austin, TX, September 20-22, 2017

  • El-Hadedy, Mohamed; Mihajloska, Hristina; Gligoroski, Danilo; Kulkarni, Amit; Stroobandt; Dirk; Skadron,
  • Kevin. A 16-bit Reconfigurable Encryption Processor for Pi-Cipher. 23rd Reconfigurable Architectures

Workshop, Co-located IPDPS 2016 . (Best Paper Award)

  • Kevin Angstadt Jack Wadden Xiaoping Huangy Mohamed El-Hadedy, Westley Weimer Kevin Skadron RAPID:

Accelerating Pattern Search Applications with Reconfigurable Hardware, TECHCON-2016, Austin, TX, September 11-14, 2016 (Best PaperAward)

  • El-Hadedy, Mohamed; Guo, Xinfei; Margala, Martin; Stan, Mircea; Skadron, Kevin, Dual-Data Rate Transpose-

Memory Architecture Improves the Performance, Power and Area of Signal-Processing Systems. Submitted to JSPS Journal. (Accepted)

  • El-Hadedy, Mohamed; Kulkarni, Amit; Stroobandt, Dirk; Skadron, Kevin, Reco-Pi: A Reconfigurable Crypto-

processor for Pi-Cipher, in Journal of Parallel and Distributed Computing, Special issue on Reconfigurable Computing Through the Looking Glass, 2016. (Accepted) (Journal, JPDC, science-direct)

  • El-Hadedy, Mohamed. Runtime Flexibility in FPGAs (Opportunities and Challenges), PhD trial lecture,

Trondheim, Norway, February 2012.

slide-12
SLIDE 12

Questions ?? Thank you

www.recoiot.com