STMBench7: A Benchmark for Software Transactional Memory Rachid - - PowerPoint PPT Presentation

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STMBench7: A Benchmark for Software Transactional Memory Rachid Guerraoui 1 Micha Kapaka 1 Jan Vitek 2 1 EPFL, Switzerland 2 Purdue University, USA EuroSys 2007 Micha Kapaka (EPFL) STMBench7 EuroSys 2007 1 / 23 Introduction Goal of

SLIDE 1

STMBench7: A Benchmark for Software Transactional Memory

Rachid Guerraoui1 Michał Kapałka1 Jan Vitek2

1EPFL, Switzerland 2Purdue University, USA

EuroSys 2007

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 1 / 23

SLIDE 2

Introduction

Goal of the Talk

1 Recall the idea of software transactional memory 2 Present STMBench7: a benchmark for STM implementations

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 2 / 23

SLIDE 3

Introduction

New Trends in Hardware

Year CPU clock speed Common (mis)interpretation

f Moore’s law. . .

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 3 / 23

SLIDE 4

Introduction

New Trends in Hardware

Year CPU clock speed ? . . . now challenged

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 3 / 23

SLIDE 5

Introduction

New Trends in Hardware

Year # cores per CPU Solution: going multi-core

⇓

New challenges for the masses of programmers:

1 Exploit parallelism 2 Manage concurrency

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 4 / 23

SLIDE 6

Introduction

Current Approaches to Multi-threading

Explicit locking is hard

Deadlock, priority inversion Fault-tolerance issues

synchronized(this) { this.x.credit(5); this.y.debit(5); } Wait-free/obstruction-free computing: not for mortals (each algorithm a PODC/DISC paper. . . )

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 5 / 23

SLIDE 7

Introduction

Software Transactional Memory (STM)

Multi-threading made easier: thread synchronization via in-memory transactions Does not share the inherent problems of locking atomic { acc1.x.credit(5); acc2.y.debit(5); } ⇒ commit or abort

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 6 / 23

SLIDE 8

Introduction

STM implementations are coming!

DSTM ASTM DSTM2 TL2 RSTM OSTM SI-STM LSA-STM SXM Haskell STM . . . Which one is best?

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 7 / 23

SLIDE 9

Introduction

Open Problems

1 Which implementation/algorithm is best? 2 What are the trade-offs? 3 Are the overheads acceptable?

⇒ Need evaluation tools theoretical experimental ⇒ STMBench7

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 8 / 23

SLIDE 10

Introduction

Evaluation So Far

Design features Simple data structures “Toy” applications ⇒ Need realistic benchmark Thread 1 Thread 2 Thread 3 Hash table R-B Tree Skip list put remove get

⇓

Total throughput

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 9 / 23

SLIDE 11

Introduction

STM Benchmark Recipe

1 Realistic workload 2 Multi-threading 3 Non-trivial concurrency 4 Baseline for comparison

+ std. benchmark requirements STMBench7 is a first step towards such a benchmark

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 10 / 23

SLIDE 12

Introduction

Example Output of STMBench7

500 1000 1500 2000 2500 3000 3500 4000 4500 5000 2 4 6 8 10 12 14 16 Maximum latency [ms] Number of threads R/T1 medium R/T1 coarse W/T2 medium W/T2 coarse

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 11 / 23

SLIDE 13

Introduction

Example Output of STMBench7

2000 4000 6000 8000 10000 12000 14000 5 10 15 20 25 30 35 Total throughput [operations / s] Number of threads medium ASTM coarse

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 11 / 23

SLIDE 14

Architecture of STMBench7

Realistic Workload

1 Realistic workload 2 Multi-threading 3 Non-trivial concurrency 4 Baseline for comparison

STMBench7 is based on the OO7 benchmark: Well-known in OO database world Aims at being realistic (CAD/CAM/CASE applications) Already used for transactional monitors Way not enough!

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 12 / 23

SLIDE 15

Architecture of STMBench7

OO7 Data Structure (Main Tree)

Module Manual CA CA CA CA . . . . . . . . . BA BA . . . 7 levels Complex Assemblies (CA) Base Assemblies (BA)

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 13 / 23

SLIDE 16

Architecture of STMBench7

OO7 Data Structure (Design Library)

BA . . . BA CP CP . . . CP Doc AP Graph . . . . . . Base Assemblies (BA) Design Library (Composite Parts CP) Atomic Parts (AP)

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 14 / 23

SLIDE 17

Architecture of STMBench7

OO7 / STMBench7 Data Structure Summary

Large tree with a graph in each leaf 6 indexes Can be traversed in any direction

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 15 / 23

SLIDE 18

Architecture of STMBench7

OO7 Limitations

OO7: Single client TTC of isolated long

perations measured

Mostly static structure Client Data structure

peration

⇓

Time to complete

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 16 / 23

SLIDE 19

Architecture of STMBench7

From OO7 to STMBench7

STMBench7: Multiple threads Various-length operations Dynamic structure OO7-related code: ∼ 50% Thread 1 Thread 2 Thread 3 Data structure

⇓

Latency, throughput

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 17 / 23

SLIDE 20

Architecture of STMBench7

Operation Types in STMBench7

Traversals: access most objects Short traversals: access object on some random path Short operations: search and/or simple updates Structure modification operations

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 18 / 23

SLIDE 21

Architecture of STMBench7

Operation Types in STMBench7

Traversals: access most objects Short traversals: access object on some random path Short operations: search and/or simple updates Structure modification operations

⇓

1 Realistic workload 2 Multi-threading 3 Non-trivial concurrency 4 Baseline for comparison

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 18 / 23

SLIDE 22

Architecture of STMBench7

Built-in Locking Techniques

1 Realistic workload 2 Multi-threading 3 Non-trivial concurrency 4 Baseline for comparison

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 19 / 23

SLIDE 23

Architecture of STMBench7

Built-in Locking Techniques

1 Realistic workload 2 Multi-threading 3 Non-trivial concurrency 4 Baseline for comparison

Coarse-grained locking: single RW lock Medium-grained locking:

ne RW lock per level,

global RW lock for structure modifications.

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 19 / 23

SLIDE 24

Architecture of STMBench7

Porting Issues

Languages: Current implementation in Java 5 (∼ 5000 lines) C# port being developed (group of M. Herlihy) C++ version coming soon (with M. Scott) STMs: Experiments done with ASTM Easy to plug other STMs (although no single STM interface)

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 20 / 23

SLIDE 25

Concluding Remarks

Summary

STMBench7 is a first attempt at realistic benchmarking STMs Data structure suggestive of CAD, CAM, CASE and similar applications, but also some on-line services Code already available (and ready for use) Open-source (BSD license) First experiments show that STMBench7 is a “stress test” for STM (see the paper)

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 21 / 23

SLIDE 26

Concluding Remarks

Open Problems (Recalled)

1 Which implementation/algorithm is best? 2 What are the trade-offs? 3 Are the overheads acceptable?

⇒ Need evaluation tools theoretical (stay tuned. . . ) experimental ⇒ STMBench7

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 22 / 23

SLIDE 27

Concluding Remarks

Open Problems (Recalled)

1 Which implementation/algorithm is best? 2 What are the trade-offs? 3 Are the overheads acceptable?

⇒ Need evaluation tools theoretical (stay tuned. . . ) experimental ⇒ STMBench7 Future directions: Add fine-grained locking Data validation

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 22 / 23

SLIDE 28

Concluding Remarks

Questions? lpd.epfl.ch/kapalka/stmbench7.php

Michał Kapałka (EPFL) STMBench7 EuroSys 2007 23 / 23