SIST PROGRAM SIST PROGRAM D-ZERO EXPERIMENT D-ZERO EXPERIMENT By - PowerPoint PPT Presentation

SIST PROGRAM SIST PROGRAM D-ZERO EXPERIMENT D-ZERO EXPERIMENT By Jefferson OKRAKU By Jefferson OKRAKU Morehouse College Morehouse College Supervised By Geoff SAVAGE Supervised By Geoff SAVAGE Control Systems Group Control Systems Group

Summer Project Summer Project Objective: Objective: To send data to the To send data to the chips on this board chips on this board from a far off location from a far off location …..and that is exactly ..and that is exactly … what happened… …. . what happened

Fermilab and its Accelerators Fermilab and its Accelerators Chicago ↓  p p 1.96 TeV Booster p CDF DØ Tevatron  p  p source Main Injector & Recycler

DØ Experiment DØ Experiment The DØ experiment is focused The DØ experiment is focused on precise studies of on precise studies of interactions of protons and interactions of protons and antiprotons at the highest antiprotons at the highest available energies. available energies. DØ detector is one of two DØ detector is one of two large particle detectors here at large particle detectors here at Fermilab. Fermilab. It’ ’s basically a camera. s basically a camera. It Can inspect Zillions of Can inspect Zillions of collisions but records just a collisions but records just a few few

DØ Detector DØ Detector Calorimeters Silicon Detector Calorimeters Silicon Detector Tracker Tracker Muon Muon System System antiprotons protons protons antiprotons Beamline Beamline Shielding Shielding Electronics (Boards are in there somewhere) Electronics (Boards are in there somewhere)

Silicon Readout Data Flow Silicon Readout Data Flow The SVX The SVX The SVX The SVX sequencer sequencer sequencer sequencer controls SVX controls SVX controls SVX controls SVX chips and chips and chips and chips and To silicon detector To silicon detector 25’ High Mass Cable 25’ High Mass Cable transfers data transfers data transfers data transfers data (3M/50 conductor) (3M/50 conductor) from the SVX from the SVX from the SVX from the SVX chips to the chips to the chips to the chips to the readout crates. readout crates. readout crates. readout crates. The SVX chips The SVX chips The SVX chips The SVX chips Optical Link Optical Link S S S S S S digitize 128 digitize 128 digitize 128 digitize 128 1Gb/s 1Gb/s E E E E E E Q Q Q Q Q Q SEQ SEQ analog inputs analog inputs analog inputs analog inputs Controller Controller Serial Command from silicon from silicon from silicon from silicon Link strip detectors. strip detectors. strip detectors. strip detectors. V V V V Platform Platform Pwr Pwr V V R R PC PC B B R R B B VME VME D D Pwr Pwr 1 1 1553 Monitoring 1553 Monitoring B B 5 5 PC PC MCH2 MCH2 5 5 3 3 MCH3 MCH3 SDAQ PDAQ PDAQ (L3) (L3) Movable counting house

Problem Problem SVX Sequencers are at an SVX Sequencers are at an obscure location on the obscure location on the detector. detector. If only we can reprogram If only we can reprogram In order to change the In order to change the the boards without going to them the boards without going to them firmware on any of the firmware on any of the physically? physically? chips, for testing or chips, for testing or otherwise, someone has otherwise, someone has to go down to the to go down to the detector. detector. To do this, they need To do this, they need permission (You can’ ’t just t just permission (You can walk onto the platform). walk onto the platform).

Programming FPGA Chips Programming FPGA Chips

FPGA and Firmware FPGA and Firmware Field Programmable Gate Field Programmable Gate Array. Array. They are semiconductor emiconductor They are s devices containing devices containing programmable logic programmable logic components called "logic components called "logic blocks", and programmable blocks", and programmable interconnects. interconnects. Firmware is a set of Firmware is a set of instructions programmed instructions programmed on an FPGA. on an FPGA. Unlike software, it is not Unlike software, it is not loaded from a disk and loaded from a disk and unlike hardware, it can be unlike hardware, it can be modified once installed. modified once installed.

How the chips are connected on How the chips are connected on the board the board JTAG (Joint Test Action Group) Chain The JTAG chain is a group of FPGAs daisy-chained together via a JTAG interface. A JTAG interface is a special four/five-pin interface added to a chip

SVX Sequencer SVX Sequencer From 1553 bus Physics Data Physics Data OUT IN The SVX Sequencer boards are 9U by 280mm circuit boards that reside in slots 2 The SVX Sequencer boards are 9U by 280mm circuit boards that reside in slots 2 through 21 of each of eight Eurocard Eurocard crates crates through 21 of each of eight

1553 Bus and Controller 1553 Bus and Controller The 1553 bus is a device The 1553 bus is a device which consists of a wire pair which consists of a wire pair that transfers data or power that transfers data or power between computer between computer components inside a components inside a computer or between or between computer computers . computers . The controller operates The controller operates according to a command list according to a command list stored in its local memory to stored in its local memory to direct the bus direct the bus To accommodate the my To accommodate the my program the 1553 driver, program the 1553 driver, the program is tailored to the program is tailored to talk to the bus bit at a time. talk to the bus bit at a time.

Diagram of Process Diagram of Process

Firmware Firmware Mike Utes Engineer @ D0 Board Designer JAM Player

The old and the new The old and the new JAMPLAYER JTAG Chain JAMPLAYER 1553 Chip 1553 Bus JTAG Chain get1553/ put1553

Software: Software: How the JAM PLAYER WORKS How the JAM PLAYER WORKS Clock (TCK) Timing (TMS) Data Input (TDI) Data Output (TDO)

How long is a millisecond ? How long is a millisecond ? (JTAG Timing) JTAG Timing) ( Power PC Number of Loops vs. Number of Loops per Millisecond processor M 68k 30000 processor 25000 20000 No. of Loops per Millisecond 15000 10000 5000 0 0.00E+00 5.00E+08 1.00E+09 1.50E+09 2.00E+09 2.50E+09 3.00E+09 3.50E+09 4.00E+09 4.50E+09 Number of Loops

Time Taken by Processor Action Size of File (Minutes: Seconds) M 68k Power PC program 1 st chip 43KB 22:07 7:47 verify 1 st chip 43KB 12:09 4:24 verify whole chain 72KB 55:23 21:18 Verify 1 st and 7 th chip 48KB 7:01 Verify 2 nd and 6 th chip 59KB 9:47 Verify 3 rd and 5 th chip 43KB 7:00 Verify 4 th chip 43KB 3:06 get1553 300 μ s 123 μ s put1553 300 μ s 120 μ s

Things I learned Things I learned How to use Unix, VXworks, Python How to use Unix, VXworks, Python How a 1553 bus and controller works How a 1553 bus and controller works How the D0 Experiment works How the D0 Experiment works

Acknowledgment Acknowledgment Geoff Savage Geoff Savage Mike Utes Mike Utes Taka Yasuda Taka Yasuda Jamieson Olsen Jamieson Olsen Mayling Wong-Squires Mayling Wong-Squires Bill Lee and Fritz Barlett Bill Lee and Fritz Barlett Elliot McCrory Elliot McCrory Dianne Engram Dianne Engram Me Me

THE END THE END No questions? No questions? NICE!!! NICE!!! Thank you. Thank you.

1553 Bus Driver and Controller 1553 Bus Driver and Controller To accommodate the a To accommodate the a program the 1553 driver, a program the 1553 driver, a program to talks to the driver program to talks to the driver bit at a time, had to be bit at a time, had to be merged with the Jam Player merged with the Jam Player Software. Software. Controller 1553 bus software Driver Altera Jam Bytecode player