Review of 3D Related Technologies for HEP Ray Yarema For the - PowerPoint PPT Presentation

Review of 3D Related Technologies for HEP Ray Yarema For the Fermilab ILC Pixel Detector Group Fermi National Accelerator Laboratory November 29, 2007 Paris, France

Outline • Introduction – – The Dream – World wide interest in 3D 3D?? • Applications – Industrial applications – HEP applications • 3D for the ILC and SLHC – Key 3D Technologies • SOI Detectors • 3D circuits of interest to HEP – Industry – Fermilab • Cost considerations • Summary LHC-ILC Workshop on 3D 2 Integration Techniques

Physicist’s Dream • Physicists have long dreamed of integrating sensors and readout electronics. • Pixel designs have progressed from hybrid designs to MAPS. • There is now an opportunity to provide further improve- ments with newer technologies (SOI detectors 1 , and 3D). L1 -Power regulation L2 -Digital circuits CMOS Chip L3-Analog circuits IC CMOS circuit (Handle) CMOS circuit Sensor Sensor (epi layer 5-20 um) Sensor 50-100 um 3D circuit with Handle Sensor sensor and several 200 nm BOX circuit layers Hybrid Pixel Detector Monolithic Active SOI (Silicon on Insulator) (total thickness with 50 um pitch bump Pixel Sensor (MAPS) detector less than 100 um) bonds Technology Developments LHC-ILC Workshop on 3D 3 Integration Techniques

3D Movement in Industry • Movement driven by several factors – 1) form factor, – 2) higher performance, – 3) heterogeneous integration, – 4) eventually lower cost. • Numerous conferences and meetings are being devoted to 3D technologies. – 3D integration for Semiconductor Integration and Packaging, Oct. 22-23, 2007, 26 talks, 3 rd annual meeting. – Technology Roadshow for 3D, MEMS, and Advanced Packaging, October 26- Nov. 7 in 5 Asian cities, 9 talks. – 3D IC Technology Symposium (EMC-3D), Netherlands, Oct. 4 th 2007, 10 talks. – ISSCC’06 Tutorial, “Introduction to 3D Integration” by K Bernstein from IBM. LHC-ILC Workshop on 3D 4 Integration Techniques

Industrial Applications • There are two 3D areas that are receiving a lot of attention. – Stacked memory chips and memory on CPU • IBM expected to provide samples later this year • Both IBM and Samsung could be in production next year (2008) Samsung – 30 um – Imaging arrays (pixelated laser drilled vias devices) in 70um chips • Working devices have been demonstrated by MIT LL, RTI, and Ziptronix • Much work is supported by DARPA RTI • Pixel arrays offer the Infrared Imager most promise for HEP projects. LHC-ILC Workshop on 3D 5 Integration Techniques

Possible Applications for 3D Technologies in HEP 50 um • Replacement for pixel bump bonding < 20 um – Finer pitch bonding – Lower cost bonding? • SOI Detectors • Higher performance pixel detectors Wire bonds Wire bonds to adjacent to adjacent – More functionality/ chip chip End of column logic pixel Serial Power Serial Powering – Smaller pixels Pixel Cell Electronics – Mixed technologies Edgeless Pixel Array LHC-ILC Workshop on 3D 6 Integration Techniques

Mixed Technology HEP Applications 3D processing can be used to integrate parts fabricated in different technologies (DEPFET,CMOS, CCD, SOI) Sensing Diode Metal layers Polysilicon - + N+ - + 3 NMOS trans. in pixel N+ Well P+ Well - + - + - + 5-20 um - + P- epi - + - + P++ substrate - + Particle DEPFET MAPS ISIS CCD Advantages of 3D for mixed technologies in HEP * DEPFET – Place peripheral CMOS electronics above DEPFETs * MAPS – Reduce PMOS devices in MAPS. Place CMOS above. * CCD – Place amplifier above each CCD (ISIS) pixel cell. Mixed technology circuits can use either CMOS or SOI for upper levels. Most people not familiar with SOI. 1) SOI mostly used for high speed and low power applications. 2) No latchup and more immune to SEU (radiation tolerant). 3) SOI very promising for Monolithic Active Pixel detectors and 3D assembly. LHC-ILC Workshop on 3D 7 Integration Techniques

SOI Wafer Fabrication • SOI has a thin silicon layer for fabrication of CMOS circuits on top of a thin buried oxide (BOX) layer which is supported on a handle wafer. • SOI wafers are very useful in 3D circuit integration and fabrication of SOI Fig. From H. Woo detectors Ion Beam Group KIGAM – The handle wafer can be high resistivity silicon in which diodes are formed by implantation through the BOX. – Vias are formed through the BOX to connect the diodes in the substrate to the CMOS circuitry in the top layer • SOITEC, France is a major producer of SOI wafers Active CMOS – Wafer diameter 100 mm -300 mm layer – SOI thickness 50 nm – 1 um (Smart Cut) – BOX thickness 100 nm – 3 um BOX • Discussion of how to best use SOI will follow later. Remaining part of Handle used as Donor wafer to be Detector layer Used again LHC-ILC Workshop on 3D 8 Integration Techniques

Consider Pixels for ILC and SLHC • The needs for future pixel applications are somewhat different. • ILC – Lowest mass possible, X o = 0.1%/layer – Very small pixels, approx 20 um x 20 um – Moderate radiation levels ~ 1.0 Mrads – Very low power • SLHC – Lowest mass possible given cooling constraints – Moderately large pixels, 50 um x 250 um (ATLAS) – Very High radiation levels ~ 100 Mrads – Relatively high power dissipation due to continuous readout • Look at the four key 3D technologies applied to ILC and SLHC – 1) Wafer thinning – 2) Interconnections, via formation and metallization – 3) Bonding, wafer to wafer or die to wafer – 4) Alignment LHC-ILC Workshop on 3D 9 Integration Techniques

Wafer Thinning Both CMOS and SOI wafers can be thinned to a point where they represent an insignificant fraction of a radiation length (X 0 ) for HEP experiments. Wafer backside Notes: CMP = Chemical Mechanical Polish Coarse grind Full wafer Coarse grind TMAH = thickness Tetra-methyl 720 um ammonium hydroxide 110 um (8" wafer) Fine grind 52 um 70 um Fine grind ~ 50 um Wet etch TMAH etch 40 um Dry etch & CMP down to BOX 20 um 6 - 10 um Typical SOI Wafer Thinning Typical CMOS Wafer Thinning (MIT LL) (Semitool) The thinner SOI wafers, however, can represent significant advantages for 3D circuit layout in some designs. LHC-ILC Workshop on 3D 10 Integration Techniques

Wafer Thinning Through wafer vias typically have an 8 to 1 aspect ratio for etched vias. Thus, in order to keep the area associated with the vias as small as possible, the wafers should be as thin as possible. This is critical for small pixel designs. Thinned SOI wafer from MIT Lincoln Laboratory Photos from MIT LL Six inch wafer thinned to 6 microns and mounted to 3 mil kapton. LHC-ILC Workshop on 3D 11 Integration Techniques

Wafer to Wafer Bonding With Mechanical Bond Only • Two processes available BCB – Adhesive bond (has temperature limits) – Oxide bond (SiO to Adhesive bonding SiO) Si oxide • Excellent mechanical bond good for handling and further processing Silicon oxide bonding • SiO bond is fast • Could use capacitive or inductive coupling (better) compared to for transmitting signals between parts. adhesives – OK for very small signals (test • Cannot be used as a inputs) bump bond replacement - – Normally either large areas or signal No electrical amplifiers are needed that require connections extra space – not good for high • Electrical connections density circuit designs in HEP. with filled vias are – Vias may be needed for power anyway formed after bonding • Used by IBM, MIT LL and others for 3D circuits with inter wafer vias. LHC-ILC Workshop on 3D 12 Integration Techniques

Die/Wafer to Wafer Bonding by Means of Electrical & Mechanical Bonds • Processes using metallic Cu Electrical pillars connection Mechanical – CuSn Eutectic connection – Cu thermocompression • Can be used to replace bump Copper thermocompression bonding for face to face bond between parts Cu • Mechanical bond strength is CuSn dependent on percent of eutectic Sn surface area used for bonding CuSn eutectic bond – Most applications to • Pillars on each part to be bonded are typically 5 um tall date have had large – 10 um of copper covering 75% of bond surface coverage (~75%) represents 0.075 Xo • Good alignment is more • Unacceptable for ILC difficult since parts have to • Large coverage can create unwanted paracitics be held in place during • Could be acceptable for SLHC heating process – Need to reduce copper to ~10% coverage for ILC • 10% may not provide sufficient mechanical strength • Used by IZM, RTI, and • 10% coverage may result in very uneven surface for others thin parts • Under fill with BCB may be necessary for strength and support LHC-ILC Workshop on 3D 13 Integration Techniques