Programmability in the Era of Parallel Computing Per Stenstrm - - PowerPoint PPT Presentation

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Programmability in the Era of Parallel Computing Per Stenstrm - - PowerPoint PPT Presentation

Feb 03, 2024 183 likes •287 views

Programmability in the Era of Parallel Computing Per Stenstrm Department of Computer Science and Engineering Chalmers University of Technology Sweden Multicore Scaling Cores/chip 100s cores 16 cores Source: Computer Performance : Game

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Programmability in the Era of Parallel Computing

Per Stenström Department of Computer Science and Engineering Chalmers University of Technology Sweden

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Multicore Scaling

By 2020, several hundreds of powerful cores/chip

1990 2000 2014

1 core 16 cores 100s cores

2020

Source: Computer Performance : Game Over or Next Level” IEEE Computer, Jan 2011 Predictions

Cores/chip

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Programmability

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High-Productivity Software Design in the Multi/Many-core Era

Plug & play Productivity programming languages (e.g. C/C++, Java)

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End user Productivity programmers Efficiency programmers

System-near programming

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High-Productivity Software Stack for Multi/Many-core Systems

Software Components Oblivious to Parallelism Runtime with Parallelism Capabilities Hardware Primitives (e.g. TM)

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Computer architects Efficiency-only programmers Productivity programmers

Increased level of abstraction

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Topic 1: Task based programming models

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Task-based Dataflow Prog. Models

TaskA TaskC TaskB

#pragma css task output(a) void TaskA( float a[M][M]); #pragma css task input(a) void TaskB( float a[M][M]); #pragma css task input(a) void TaskC( float a[M][M]);

  • Programmer annotations for task dependences
  • Annotations used by run-time for scheduling
  • Dataflow task graph constructed dynamially

Hypothesis: Programmers focus on extracting parallelism, system delivers performance. BUT: Is this a good idea?

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Topic 1: Transactional memory

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Transactional Memory (TM)

  • Transactional memory semantics:

– Atomicity, consistency, and isolation – Tx_begin/Tx_end primitives

  • Allow for concurrency inside critical

sections

  • Software implementations too slow
  • Hardware implementations complex but

have been adopted (IBM Bluegene, Intel Haswell)

  • 100s of papers in the open literature;

design space fairly well understood

WA RA Commit RA Re-execution TX1 TX2 Data conflict

Hypothesis: Simplifies for programmers, but is this a good idea?