Power Grid Analysis with Hierarchical Support Graphs Xueqian Zhao - - PowerPoint PPT Presentation

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Power Grid Analysis with Hierarchical Support Graphs Xueqian Zhao Jia Wang Zhuo Feng Shiyan Hu

Design Automation Group 2011 International Conference on Computer-Aided Design (ICCAD)

2 Vdd Vdd Vdd Vdd

• Multi-layer interconnects are modeled as 3D RC network

– Switching gate effects are modeled by time-varying current loadings

• DC analysis solves linear system
• Transient analysis solves

Power Grid Modeling & Analysis

Tens of millions

• f unknowns !

( ) ( ) ( ) dv t G v t C b t dt ⋅ + ⋅ = r r r

G v b ⋅ = r r

1 1

: : : :

n n n n n n

G C v b

× × × ×

∈ℜ ∈ℜ ∈ℜ ∈ℜ r r

Conductance Matrix Capacitance Matrix Node Voltage Vector Current Loading Vector

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Prior power grid analysis approaches

–Direct methods (LU factorization, Cholesky decomposition) – Cholmod uses 7GB memory and >1,000 s for a 9-million grid –Iterative methods –Preconditioned conjugate gradient (T. Chen et al, DAC’01) –Multigrid methods (S. Nassif et al, DAC’00) –Stochastic method –Random walk (H. Qian et al, DAC’05)

Prior Work

VDD VDD VDD VDD

Random walk Multigrid Direct Method

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Key observation on power grid designs

– The degree of freedom of each power grid node is relatively low

Support-graph preconditioners (SGP)

– Finding maximum spanning tree in the original grid is efficient – Factorizing the spanning tree matrix is much cheaper than the original matrix – Cost: zero new fill-ins (linear time and space complexity) – Robustness: very effective for ill-conditioned systems – Suitable for both regular/irregular grids (multigrid/Poisson solvers may fail) – Good for conventional/incremental power grid analysis

1 2 3 4 5 1 9 8 7 6 4 2 4 6 5 4 9 8 1 3 3

1 2 3 4 5 6 7 8 9

2 1 2 4 3 4 8 1 6 4 3 6 5 1 8 5 3 4 9 1 9 4 3 4 d d d d d d d d d ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦

Support-Graph Preconditioner

1 1 4 2 4 6 5 4 9 8 1 3 3 2 3 6 5 4 7 8 9

1 2 3 4 5 6 7 8 9

' 2 2 ' 4 4 ' 8 ' 6 4 6 ' 5 8 5 ' 4 ' 9 9 ' 4 4 ' d d d d d d d d d ⎡ ⎤ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ ⎦

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Support-Graph Preconditioner (cont.)

SG preconditioner (P) can well approximate the original matrix (G)

– Matches well the dominant eigenvalues – Existing matrix solvers can be used directly – Allows easy multi/many-core parallel computations – Parallel GPU-based MST algorithms can handle 5M grid nodes in 1s

The condition number of P-1G can be greatly reduced

– Effectively reduces the number of Krylov-subspace iterations Matrix 1st 2nd 3rd 4th 5th 6th cond G 26.170 23.182 17.572 11.514 9.373 6.673 135.948 P 25.239 23.540 17.579 10.909 9.865 6.822 16.752 P-1G 1.431 1.204 1.062 1.000 1.000 1.000 17.442

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Condition number of matrix pencil (G,P) The support of (G,P) is defined as:

– P and G can decomposed into P=P1+P2+… and G=G1+G2+… – are positive semi-definite matrices – Eigenvalues of (G,P) are bounded by – Achieve the similar power dissipations in resistive networks

Support-Graph Preconditioner (Cont.)

max min

( , ) ( , ) ( , ) G P k G P G P λ λ =

( , ) min{ | ( ) 0, all }

T n

G P x P G x x σ τ τ = ∈ℜ − ≥ ∈ℜ

i i

P G τ −

τ

T

x Px

Power dissipated by P:

T

x Gx

Power dissipated by G:

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Hierarchical Support Graphs

Support graph for each grid partition Block-level support graph – Use the strongest edge between two blocks to connect them

Top level spanning tree Spanning tree inside a block Block-partitioned power grid example

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Include several strongest links between two blocks

– Balance the effectiveness and computational cost of HSG preconditioners – Slightly increase the number of non-zeros in preconditioner matrix factors – P is also known as the ultra-sparsifier of matrix G

Modified Hierarchical Support Graph (Cont.)

• 1. Extract the block-level SG

Block-level support graph Inner-block support graph

• 2. Each block level edge is replaced by

several strong edges from original graph

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Modified grid needs to be solved in a much faster way

– Low-rank matrix factor update through direct method can be very costly – Iterative methods need the preconditioners to be efficiently updated

Support-graph preconditioner updates

– Global grid modifications: need to update (factor) for the global SG – Local grid modifications: only need to update (factor) for the block SGs

Incremental Analysis

Blk 1 Blk 2 Blk 3 Blk 4

Blk 1 Blk 2 Blk 3 Blk 4

Preconditioner update for Incremental analysis (local grid modifications)

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CKT SG Setup Time #iteration SGPCG Solve Time ibmpg2 0.148 38 0.286 ibmpg3 1.178 68 3.884 Ibmpg4 1.503 28 2.418 Ibmpg5 1.161 212 11.4 ibmpg6 1.944 172 14.2 ibmpg7 1.385 100 9.746 ibmpg8 2.453 104 11.1

Experimental Results: Original SGPCG

Transient analysis

– Requires only one or two iterations for each time step – Can be further improved by scaling capacitance values in the SG

DC analysis result (shown in seconds)

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CKT HSGPCG Modified HSGPCG ibmpg2 52 (5.0X) 49 (6.9X) ibmpg3 112 (4.5X) 106 (5.1) Ibmpg4 83 (5.5X) 79 (7.2X) Ibmpg5 182 (2.0X) 150 (2.7X) ibmpg6 208 (1.4X) 158 (1.8X) ibmpg7 120 (2.8X) 101 (2.9X) ibmpg8 122 (2.6X) 102 (2.8X)

Experimental Results: Hierarchical SGPCG

About the modified HSGPCG solver

– Requires extra 1 MB memory for the largest CKT – Results in much better convergence for ill-conditioned matrices

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Updated block support-graph proconditioner

– Values of 20% resistors are changed by 50% – Using the original SG preconditioner may need much more iterations

CKT Updated Block SGPCG

Re-factor (s) #iter. Re-solve (s) Speedup

ibmpg2 0.012 9 0.067 20.5X ibmpg3 0.053 18 0.748 22.5X Ibmpg4 0.047 18 0.699 29.9X Ibmpg5 0.043 32 2.079 6.8X ibmpg6 0.071 24 2.475 9.1X ibmpg7 0.060 19 1.708 20.5X ibmpg8 0.058 13 1.380 24.0X

Experimental Results: Incremental Analysis

Original Block SGPCG

#iter. Re-solve (s) Speedup 15 0.087 18.8X 41 2.375 7.6X 29 1.313 17.1X 85 3.661 3.9X 50 4.737 4.9X 674 72.380 0.5X 39 3.320 10.4X

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Support-circuit preconditioners

– Leverage existing parallel Krylov-subspace solvers (GMRES)

– Solve extremely large-scale nonlinear circuits

– E.g. clock networks, power delivery networks, memory blocks, etc

LDO LDO LDO LDO

Analog Circuit Blocks Digital Circuit Blocks

LDO LDO LDO LDO

Support-Circuit Preconditioner Original Circuit with Analog and Digital Blocks

Future Work: Support-Circuit Preconditioner

Power Delivery Networks with LDOs