Performance-relevant Parameters for Reconfigurable Processors Lars - PowerPoint PPT Presentation

Classifying and Evaluating Performance-relevant Parameters for Reconfigurable Processors Lars Bauer, Muhammad Shafique, and Jörg Henkel Chair for Embedded Systems (CES) University of Karlsruhe L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

2 Development of Embedded Systems � Typical: � Static analysis of hot spots � Building tightly optimized system � Nowadays: � Increasing complexity � More functionality � Problem: � Statically chosen design point has to match all requirements � Typically inefficient for individual components (e.g. tasks or hot spots) L. Bauer Talk @ MPSoC’09, August 7 th SoC oC oC oC oC oC oC o ’0 C ’0 09, 9, 9, 9, 9, , A Aug ug ug ug ug ug ug ug ug ug ug g g g gus us us us us us us us us us us us us us us us us us ust 7 th s th th th th th th th th th th th th th th th th th th th th th th h h h h h http://ces.univ-karlsruhe.de/bauer_l ht ht ht ht ht ht ht ht ht ht ht ht http t tp tp tp tp tp tp tp tp tp tp tp tp p / :/ :/ :/ :/ :/ :/ :/ :/ :/ :/ :/ :/ ://c /c /ces /c /c /c /c /c /c /c /c /c /c es es u es es es es es es es es es es .u i .u .u .u .u ni ni ni ni ni ni ni ni ni ni niv-ka ni ni ka ka l ka ka ka ka ka ka ka ka ka ka rl rlsr rl rl rl rl rl rl rl rl rl rl rl sr sr sr sr sr sr sr sr sr sr sr sr h uh uh uh uhe. uh uh uh uh uh uh uh uh uh e. e. e. e.de de de/b de de de de de de de de de de /b /b /b /b /bau /b /b /b /b /b /b /b /b au au au au au au au au au au auer au er er er l er er er er er er er er er _

3 Possible Solution: Extensible Processors Efficiency: Mips/$, MHz/mW, Mips/area , … “ Hardware solution ” olution ” n Reconfigurable Compu- ASIC: - Non-programmable, mable, ting: Processor with - highly specialized ized reconfigurable ISA, i.e. reconfigurable - Instruction set extension - Instruction set extension - parameterization - parameterization Special Instructions ASIP SIP - inclusion/exclusion of - inclusion/exclusion of lusio (extensible nsible functional blocks functional blocks processor) essor) “ Software General purpose solution ” processor Flexibility, 1/time-to- market, … L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

4 Related Work: Reconfigurable Processors � [CoMPARE’98]: � Fine-grained reconfigurable fabric coupled to the core pipeline � Can implement a single Special Instruction (SI) at a time � [CHIMAERA’00]: � Supports multiple SIs in the reconfigurable fabric at the same time � [MOLEN’04]: � Can be configured to support only a single or multiples SIs at the same time � [RISPP’07]: � Supports multiple SIs at the same time and allows multiple (hardware) implementations per SI (providing different performance/area trade-offs) � Partitions SIs into Data Paths which are reconfigured independently � Coarse-Grained Reconfiguration: ADRES, etc. (not the focus of this talk) L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

5 Outline � Introduction � Related Work � Reconfigurable Processor Alternatives � Special Instruction-Based Categorization � Relevant Architectural Parameters � Design Space Exploration Tool � Conclusion L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

6 SI-Based Categorization � Providing Special Instruction (SI) Implementations: � How many SIs may be available at the same time? � How many implementation alternatives exist per SI? � Note: each SI may be executed by the ISA of the core pipeline � Technical constraints: Rectangular implementation of a hardware description (e.g. an SI) � The typical shape for place & route tools � These rectangular implementations cannot be placed at arbitrary positions within the reconfigurable fabric � They are typically aligned to dedicated communication ports that are provided at fixed positions L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

SI-Based Categorization Overview 7 How many SIs at Changing number of SIs with At most 1 SI with a At most n>1 SIs with a fixed different sizes (e.g. 2 big SIs or 5 the same How fixed maximum size maximum size per SI small SIs); maximum number of time many Imple- total data paths (DPs) mentations per SI Category-1: Single SI Category-2: Multiple SI Containers Category-3: Multiple One Implemen- Container overlapping SIs tation per SI. Core Pipeline Core Pipeline Core Pipeline SI has to be loaded completely before it is executable Category-4: Single Category-5: Multiple Partitioned Category-6: Multiple DP Containers Partitioned SI Container SI Containers Multiple Implemen- tations per SI. Core Pipeline Core Pipeline Core Pipeline SIs are partitioned into Data Paths (DPs) Reconfigu- Special Instruction rable area: Container (SIC): Core Pipeline Legend: (scaled down): Communica- Data Path Con- tion System: tainer (DPC): L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

SI-Based Categorization: 8 Category-1: Single SI Container � At most one SI is available in Core Pipeline hardware at a given time � Relatively long reconfiguration time, depending on the size of the SI Container � Depending upon the required � Corresponds to amount of logic two SIs might fit into [CoMPARE’98] the Container, but it is not supported � � Internal fragmentation Core Pipeline Reconfigu- Special Instruction Legend: (scaled down): rable area: Container (SIC): L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

SI-Based Categorization: 9 Category-2: Multiple SI Containers � An SI may be loaded Core Pipeline into any free container � SIs may not be bigger than the container, even if not all containers are demanded � Corresponds to � � � external fragmentation [CHIMAERA’00] (in addition to the and [MOLEN’04] internal fragmentation per SI Container) Core Pipeline Reconfigu- Special Instruction Legend: (scaled down): rable area: Container (SIC): L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

10 Example: Modular SIs (using Data Paths) DCT=0 HT=0 DCT=0 HT=1 INPUT: OUTPUT: + + + SAV (Sum of QSub Repack Transform Absolute Values) DCT HT ≥ 0 Y 00 + − neg X 1 X 00 >> 1 + + ≥ 0 − X 30 << 1 Y 10 neg X 2 >> 1 + ≥ 0 Y >> 1 − neg X 3 << 1 Y 30 X 10 − + ≥ 0 + + X 20 >> 1 neg X 4 Y 20 L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

SI-Based Categorization: 11 Category-3: Multiple overlapping SIs � There is no predetermined maximum of supported SIs Core Pipeline � Multiple SIs may share common data paths (i.e. reuse them) because at most one SI is executed at a time. � This addresses the internal and external fragmentation problem � Demand for internal communication system Reconfigu- Special Instruction rable area: Container (SIC): Core Pipeline Legend: (scaled down): Communica- Data Path Con- tion System: tainer (DPC): L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

SI-Based Categorization Overview 12 How many SIs at Changing number of SIs with At most 1 SI with a At most n>1 SIs with a fixed different sizes (e.g. 2 big SIs or 5 the same How fixed maximum size maximum size per SI small SIs); maximum number of time many Imple- total data paths (DPs) mentations per SI Category-1: Single SI Category-1: Single SI Category-2: Multiple SI Containers Category-2: Multiple SI Containers Category-3: Multiple Category-3: Multiple One Implemen- Container Container overlapping SIs overlapping SIs tation per SI. Core Pipeline Core Pipeline Core Pipeline Core Pipeline Core Pipeline Core Pipeline e n e n e n SI has to be loaded completely before it is executable o o o Category-4: Single Category-5: Multiple Partitioned Category-6: Multiple DP Containers Partitioned SI Container SI Containers Multiple Implemen- tations per SI. Core Pipeline Core Pipeline Core Pipeline SIs are partitioned into Data Paths (DPs) Reconfigu- Special Instruction rable area: Container (SIC): Core Pipeline Legend: (scaled down): Communica- Data Path Con- tion System: tainer (DPC): L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l

Example: Modular SIs 13 (allowing for multiple Implementations) DCT=0 HT=0 DCT=0 HT=1 INPUT: OUTPUT: + + + SAV (Sum of QSub Repack Transform Absolute Values) � The ‘Transform’ Data path might be available once (i.e. readily reconfigured) and used 8 times to realize the SI functionality � Or it might be available twice and both instances are used 4 times, or … L. Bauer Talk @ MPSoC’09, August 7 th http://ces.univ-karlsruhe.de/bauer_l