Outline Processors and Instruction Sets Review of pipelining - PowerPoint PPT Presentation

Advanced Topics on Heterogeneous System Architectures Pipelining � Politecnico di Milano � Seminar Room @ DEIB � 30 November, 2017 � Antonio R. Antonio R. Miele Miele � Marco D. Santambrogio Marco D. Santambrogio � Politecnico di Milano �

2 Outline � • Processors and Instruction Sets � • Review of pipelining � • MIPS � – Reduced Instruction Set of MIPS ™ Processor � – Implementation of MIPS Processor Pipeline � – The Problem of Pipeline Hazards � – Performance Issues in Pipelining � 2

3 Main Characteristics of MIPS ™ Architecture � • RISC (Reduced Instruction Set Computer) Architecture � Based on the concept of executing only simple instructions in a reduced basic cycle to optimize the performance of CISC CPUs. � • LOAD/STORE Architecture � ALU operands come from the CPU general purpose registers and they cannot directly come from the memory. � Dedicated instructions are necessary to: � – load data from memory to registers � – store data from registers to memory � • Pipeline Architecture: � Performance optimization technique based on the overlapping of the execution of multiple instructions derived from a sequential execution flow. �

4 A Typical RISC ISA � • 32-bit fixed format instruction (3 formats) � • 32 32-bit GPR (R0 contains zero, DP take pair) � • 3-address, reg-reg arithmetic instruction � • Single address mode for load/store: � base + displacement � – no indirection � • Simple branch conditions � • Delayed branch � • Example: SPARC, MIPS, HP PA-Risc, DEC Alpha, IBM PowerPC, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3 �

5 Approaching an ISA � • Instruction Set Architecture � – Defines set of operations, instruction format, hardware supported data types, named storage, addressing modes, sequencing � • Meaning of each instruction is described by RTL on architected registers and memory � • Given technology constraints assemble adequate datapath � – Architected storage mapped to actual storage � – Function units to do all the required operations � – Possible additional storage (eg. MAR, MBR, …) � – Interconnect to move information among regs and FUs � • Map each instruction to sequence of RTLs � • Collate sequences into symbolic controller state transition diagram (STD) � • Implement controller �

6 Example: MIPS � Register-Register 6 5 11 10 31 26 25 21 20 16 15 0 Op Rs1 Rs2 Rd Opx Register-Immediate 31 26 25 21 20 16 15 0 immediate Op Rs1 Rd Branch 31 26 25 21 20 16 15 0 immediate Op Rs1 Rs2/Opx Jump / Call 31 26 25 0 target Op

7 Datapath vs Control � Datapath Controller signals Control Points Datapath: Storage, FU, interconnect sufficient to perform the • desired functions Inputs are Control Points – Outputs are signals – Controller: State machine to orchestrate operation on the data path • Based on desired function and signals –

8 Datapath vs Control � Control BUS Data BUS Address BUS CPU Data Control Unit Data path PSW InstrucHon ALU IR Registri Memory Control PC

9 The code… � … … … … … 0789 load R02,4000 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 0793 add R01,R01,R02 0794 store R01,4000 … … … … …

10 Starting scenario � CPU Memory Data path Control Unit … … … … … 0789 load R02,4000 ALU PSW 0790 load R03,4004 InstrucHon 0791 add R01,R02,R03 0792 load R02,4008 IR Register 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … R05 PC R04 0789 R03 … … … … … 4000 1492 R02 Data 4004 1918 R01 4008 2006 R00 … … … … … Address BUS Contro BUS Data BUS

11 Read Instruction 0789 � Memory CPU Data path Control Unit … … … … … Reading load R02,4000 0789 load R02,4000 ALU PSW InstrucHon 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … R05 PC R04 0790 0789 0789 +1 R03 … … … … … 4000 1492 Data R02 4004 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

12 Exe Instruction 0789 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 InstrucHon ALU PSW 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R02,4000 4000 R05 PC R04 0790 R03 … … … … … Data 4000 1492 1492 R02 4004 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

13 Read instruction 0790 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 InstrucHon ALU PSW load R03,4004 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R02,4000 R05 PC R04 0790 0791 0790 +1 R03 … … … … … Data 4000 1492 R02 1492 4004 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

14 Exe Instruction 0790 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 InstrucHon ALU PSW 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R03,4004 4004 R05 PC R04 0791 R03 … … … … … Data 4000 1492 R02 1492 4004 1918 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

15 Read Instruction 0791 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 InstrucHon ALU PSW 0790 load R03,4004 0791 add R01,R02,R03 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R03,4004 R05 PC R04 0792 0791 +1 0791 R03 … … … … … Data 1918 4000 1492 R02 1492 4004 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

16 Exe Instruction 0791 � Memory CPU Data path Control Unit … … … … … ackt 0789 load R02,4000 ALU PSW InstrucHon 3410 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 add 0794 store R01,4000 … … … … … … add R01,R02,R03 R05 PC R04 0792 R03 … … … … … 1918 1918 4000 1492 Data R02 1492 1492 4004 1918 R01 4008 2006 R00 … … … … … Address Bus Contro bus Data Bus

17 Read Instruction 0792 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 InstrucHon ALU PSW 0790 load R03,4004 0791 add R01,R02,R03 load R02,4008 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … add R01,R02,R03 R05 PC R04 0793 0792 +1 0792 R03 … … … … … Data 1918 4000 1492 R02 1492 4004 1918 R01 4008 2006 3410 R00 … … … … … Address Bus Contro bus Data Bus

18 Exe Instruction 0792 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 ALU PSW InstrucHon 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R02,4008 4008 R05 PC R04 0793 R03 … … … … … 1918 4000 1492 Data R02 1492 4004 1918 R01 4008 2006 2006 3410 R00 … … … … … Address Bus Contro bus Data Bus

19 Read Instruction 0793 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 ALU PSW InstrucHon 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri add R01,R01,R02 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … load R02,4008 R05 PC R04 0793 +1 0793 0794 R03 … … … … … 1918 4000 1492 Data R02 2006 4004 1918 R01 4008 2006 3410 R00 … … … … … Address Bus Contro bus Data Bus

20 Exe Instruction 0793 � Memory CPU Data path Control Unit … … … … … ack 0789 load R02,4000 5416 ALU PSW InstrucHon 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 add 0794 store R01,4000 … … … … … … add R01,R01,R02 R05 PC R04 0794 R03 … … … … … 1918 4000 1492 Data R02 2006 2006 4004 1918 R01 4008 2006 3410 3410 R00 … … … … … Address Bus Contro bus Data Bus

21 Read Instruction 0794 � Memory CPU Data path Control Unit … … … … … Reading 0789 load R02,4000 ALU PSW InstrucHon 0790 load R03,4004 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 store R01,4000 0794 store R01,4000 … … … … … … add R01,R01,R02 R05 PC R04 0795 0794 +1 0794 R03 … … … … … 1918 4000 1492 Data R02 2006 4004 1918 R01 4008 2006 5416 R00 … … … … … Address Bus Contro bus Data Bus

22 Exe Instruction 0794 � CPU Memory Data path Control Unit … … … … … writing 0789 load R02,4000 ALU PSW 0790 load R03,4004 InstrucHon 0791 add R01,R02,R03 0792 load R02,4008 IR Registri 0793 add R01,R01,R02 0794 store R01,4000 … … … … … … store R01,4000 4000 R05 PC R04 0795 R03 … … … … … 1918 4000 1492 R02 Data 2006 4004 1918 R01 4008 2006 5416 5416 R00 … … … … … Address Bus Contro bus Data Bus