Outline Introduction. Paper: Paper: Optimal Sizing for Minimum - PowerPoint PPT Presentation

Paper presentation – Ultra-Portable Devices Outline • Introduction. Paper: Paper: • Optimal Sizing for Minimum Energy. B Benton H. C., Alice Wang, et al. t H C Ali W t l • Standard Cell and Minimum Energy. Device Sizing for Minimum Energy Operation in Subthreshold Circuits, IEEE Custom Integrated Circuits Conference, Date: 2004. • Measured Results. • Summary. Presented by: S. M. Yasser Sherazi Paper Presentation - Ultra Portable Devices 1 Paper Presentation - Ultra Portable Devices 2 2 ” Introduction ” ’’Optimal Sizing for Minimum Energy’’ • Minimum energy operation for low performance situations occurs in the • Sizing influences the energy consumption of a circuit in subthreshold region . subthreshold region twoprimary ways. t i • Increasing leakage energy at low supply voltages offsets the reduced g g gy pp y g • First, sizing directly affects energy consumption by changing Fi t i i di tl ff t ti b h i active energy and causes a minimum energy point. switched capacitance and leakage current. • Many designs exhibit a minimum energy operating point higher than the Man designs e hibit a minim m energ operating point higher than the minimum achievable VDD. • Secondly, sizing affects the minimum voltage at which the circuit functions which can change the absolute minimum circuit functions, which can change the absolute minimum • This operating point is a function of several parameters. energy point. • In general, designs with larger leakage energy relative to active energy have a higher optimum VDD. Paper Presentation - Ultra Portable Devices 3 Paper Presentation - Ultra Portable Devices 4

” Sizing for a given V DD ” ” Sizing for a given V DD ” • Theoretically optimal minimum energy circuits should use minimum sized • For a single inverter, dynamic ( E DYN ), leakage ( E L ), and total devices devices energy ( E T ) per cycle are expressed, assuming rail-to-rail ( E ) l d i il t il • The propagation delay of a characteristic inverter with a certain switched swing ( V GS =V DD for "on" current). capacitance Cg= α C L in subthreshold, where α is activity factor and C L is the load capacitance assuming average • • Total energy per cycle is proportional to C g , so minimum sized fanout devices give a minimum C g and minimize E T for a single devices give a minimum C and minimize E for a single K is a delay fitting parameter. K is a delay fitting parameter • • The terms Io,g and V Tg are fitted parameters that do not correspond exactly inverter at a given VDD. • with the MOSFET parameters. Paper Presentation - Ultra Portable Devices 5 Paper Presentation - Ultra Portable Devices 6 ’ Sizing for a given V DD ” ” Sizing for a given V DD ” • Assuming a critical path depth of L DP characteristic inverter delays gives an operating frequency, f = (t d L DP ) -1 . f d l i ti f (t L ) 1 • Minimum sized devices generally minimize energy • The inverter capacitance and leakage current to define total consumption in subthreshold for a given V DD . switched capacitance, C eff = KC g , and total leakage width, switched capacitance C = KC and total leakage width W eff • However, sizing also impacts the minimum operating voltage, • Assuming that the majority of gates in a typical design are • Assuming that the majority of gates in a typical design are which can affect the total energy per operation, E T . hich can affect the total energ per operation E sized similarly, a universal increase in transistor sizes will increase both C eff and W eff , raising power. eff , g p eff Paper Presentation - Ultra Portable Devices 7 Paper Presentation - Ultra Portable Devices 8

’’ Sizing and Minimum operating ” Sizing and Minimum operating Voltage ’’ Voltage Voltage Voltage ” • Minimum VDD operation occurs • Fig. (a) shows the VTC of a 9-stage ring oscillator output. when the PMOS and NMOS when the PMOS and NMOS devices have the same current • Fig. (b) shows output at the minimum V DD for the typical corner (simulation). • Fig. shows the minimum voltage • Optimum PMOS/NMOS width ratio of 12 is shown with others for for which a ring oscillator comparison. maintains 10% 90% voltage maintains 10%-90% voltage swing. • The optimum PMOS/NMOS width across all process corners is 12. Paper Presentation - Ultra Portable Devices 9 Paper Presentation - Ultra Portable Devices 10 ’’ Sizing and Minimum operating ’’Standard Cells and Minimum Energy’’ Voltage Voltage’’ • Sizing an inverter to have a switching threshold at V DD /2 gives a good • Most standard cell libraries focus on high performance. estimate of the optimum width to minimize V estimate of the optimum width to minimize V DD because the NMOS and because the NMOS and • Lower power cells generally use smaller sizes. L ll ll ll i PMOS are balanced. • Standard cell library for low power uses branch-based static logic to reduce p parasitic capacitances and a reduced set of standard cells. p • This simulation shows NMOS and PMOS current for the equivalent circuit • Fig. shows mini operating voltages for standard cell functionality in on the right in the inset for V DD =70mV synthesized, parallel and programmable FIR filter using normal cell selection over process comers (simulation) selection over process comers (simulation). Paper Presentation - Ultra Portable Devices 11 Paper Presentation - Ultra Portable Devices 12 12

’’Standard Cells and Minimum Energy’’ ‘’ Standard Cells and Minimum Energy ’’ • Fig. shows a schematic of the D-flip-flop. In the standard implementation, • Fig. shows the lowest operating voltage for the cells in the all of the inverters use small NMOS and only slightly larger PMOS devices all of the inverters use small NMOS and only slightly larger PMOS devices minimum-V DD FIR filter. i i V FIR filt except I3, which is several times larger to reduce C-Q delay. • The number of cell types has reduced, and all of the cells work • In order to operate the DFF in all corners, the size of I3 is reduced and I6 is at 300mV across all corners. at 300mV across all corners strengthened. Clearly, the larger feedback inverter creates some energy overhead. • Standard cell functionality in synthesized FIR filter using cells • The resized flip flop can operate at 300mV at all process comers in The resized flip-flop can operate at 300mV at all process comers in sized to minimize V sized to minimize V DD , over process comers (simulation). over process comers (simulation) simulation. Paper Presentation - Ultra Portable Devices 13 13 Paper Presentation - Ultra Portable Devices 14 14 ” Measurement Results” ” Measurement Results” • Fig. shows the measured performance versus V DD , for the two filters using A 0.18 µm, 6M layer, 1.8V , 7mm 2 test chip was fabricated to measure the 2 t their respective critical path ring oscillators and the LFSR data to produce their respective critical path ring oscillators and the LFSR data to produce • A 0 18 6M l 1 8V 7 t hi f b i t d t th one pseudorandom input per cycle. impact of sizing on minimum energy operation of standard cells. • The minimum-V DD filter exhibits a 10% delay penalty over the standard filter. • The test chip features two programmable 8-tap FIR filters. Both filters • Both filters operate in the range of 3kHz to 5MHz over V DD values of 150mV produce non-truncated 19-bit outputs. to 1V. to 1V. • Both filters are fully functional to below 200mV. • The first filter was synthesized using the unmodified synthesis flow and normal cells. • The second filter was synthesized using the modified flow in which some cells were omitted and some cells were resized to minimize VDD. cells were omitted and some cells were resized to minimize VDD Paper Presentation - Ultra Portable Devices 15 15 Paper Presentation - Ultra Portable Devices 16 16

” Measured energy per operation of the ”Measurement Results” FIR filters on the test chip FIR filters on the test chip ” • Fig(a). shows an oscilloscope plot of the standard filter working correctly at V V DD =150mV. =150mV • The reduced drive current and large capacitance in the output pads of the chip cause the slow rise and fall times in the clock, but the signal is still full swing. One bit of the output is shown. • Fig(b). shows plot of the clock output for V DD = 65mV. Paper Presentation - Ultra Portable Devices 17 Paper Presentation - Ultra Portable Devices 18 ” Annotated die photo of 0. I8pm ”Summary” subthreshold FIR test chip subthreshold FIR test chip ” • For typical circuits and modem technologies, the optimum supply voltage for minimizing power is higher than the failure point for minimum sized for minimizing power is higher than the failure point for minimum sized devices at the typical corner. • Thus, minimum sized devices are theoretically optimal for minimizing power. Even if the minimum energy point for a certain process corner or unusual circuit occurs at a supply voltage where minimum sized devices unusual circuit occurs at a supply voltage where minimum sized devices cannot function. • Existing static CMOS standard cell libraries function well in subthreshold. • • Resizing or restricting cell usage in such libraries can lower the worst- Resizing or restricting cell usage in such libraries can lower the worst case minimum V DD , but the overhead increases energy consumption at the typical corner. Paper Presentation - Ultra Portable Devices 19 Paper Presentation - Ultra Portable Devices 20