SLIDE 13 So Softwar tware e ar archit chitectur ecture
Bare-metal with drivers
OR W Wirel eless ss Proce
sing Plane ne
deterministic signal processing blocks, header parsing, channel resource scheduling, multicore fifo queues, sample I/O blocks
OR Wi Wirele eless ss Decisio ision n Plan ane
protocol state machine, flowgraph composition, block configurations, knowledge plane, RFE control logic
OR R Runtime ime System em
compute resource scheduling, deterministic execution ensuring protocol deadlines are met
data i n data
t monitor & co ntr
16
RFE BBU (Digital) (Analog) AX