Outline Introduction. Paper: System Design for Ultra-Low Power. - - PowerPoint PPT Presentation

Paper presentation – Ultra-Portable Devices

Paper: Presented by:

Bernier, C. Hameau, F., et al. An Ultra Low Power SoC for 2.4GHz IEEE802.15.4 wireless communications, Solid-State Circuits Conference,

• 2008. ESSCIRC 2008. 34th European, On page(s):

426 - 429, Publication Date: 15-19 Sept. 2008

• S. M. Yasser Sherazi

2009-08-27 1 Paper Presentation - Ultra Portable Devices

Outline

• Introduction.
• System Design for Ultra-Low Power.
• Digital Design for Ultra-Low Power.
• RF/Analog Design for Ultra-Low Power.
• Measurement Results.
• Summary.

2009-08-27 2 Paper Presentation - Ultra Portable Devices

” Introduction 1/2”

• IEEE802.15.4, 2.4GHz transceiver designed in 130nm CMOS
• A novel mini. complexity partial correlation algorithm
• At 1.2V, the RX/TX drains 5.4mW in RX and 8.1mW in TX
• 1% PER for a -81 dBm input power
• 250kbit/s data rate, the RX/TX energy efficiency is 21.5nJ/bit

RX and 32.5nJ/bit TX

2009-08-27 3 Paper Presentation - Ultra Portable Devices

” Introduction 2/2”

• Complete system modeling for ULP direct conversion RX/TX.
• Elementary function optimization for minimum power.
• A novel digital baseband demodulation algorithm for minimum power and

area.

• The RX/TX integrated on a SoC with an 8051 micro-controller clocked at

8MHz.

• 32kbyte memory (SRAM) & 4kbytes for user data.
• All internal clocks derived from a single 40MHz external clock.

’’SOC Architecture’’ ”System Design for ULP”

• Spreading of the 250kbps data stream into a 2Mchip/s
• Mapping 4-bit symbol onto one of 16 quasi-orthogonal Seq.
• 32-chip pseudo-random sequences.
• Chip stream is modulated using O-QPSK
• Digital part of receiver, half of the spreading codes are

complex conjugates.

• Reduced Correlation algorithm.

”System Design for ULP”

Implementation (Digital)

• Eight non-coherent 4-chip partial correlations.
• Rather than a single 32 chip correlation.
• Well suited for ULP.
• Most Complex calculation is square
• Most Multiplications are by + 1.

’’32-chip (GC) vs 8 4-chip (PC)’’

”System Design for ULP”

Implementation (Analog)

• Information in sign of baseband I and Q signal.
• Non-linear amplification used in analog RX chain.
• Reduced resolution and low sampling rate ADC.
• ADC’ sampling rate 4MS/s and 3-bit dynamic range.
• Drastic reduction of consumption of RX/TX digital operator.

’’Simulated PER vs. Input Power’’ ”Digital Design for ULP”

• Packet format for IEEE802.15.4
• 8 consective 0 symbols.
• Start Frame Delimiter (SFD).
• PBY Header (length of PSDU).
• PSDU is the payload.

’’Digital RX Architecture’’

’’Partial Correlation Algorithm’’ ∑ ∑

= = + +

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ × = =

7 2 3 * 4 4

) ( ) ( _ 15 ,.., )), ( _ max(

p k n k p k p

c s n

• ut

corr with N n

• ut

corr

• For each symbol period, the received symbol is:
• where sm is the mth complex signal sample (of 32) and cn

m is

the mth complex chip (of 32) of the nth spreading code (of 16).

’’Architecture of PC bank’’ ’’Generation of Spreading Codes’’ ’’RF/Analog Design for ULP’’

• Direct Conversion reciever architecture.
• Bandwidth of baseband chain is minimized.
• Amplifier’s outout impedence can be increased.
• Its bias current is decreased withot sacrificing gain.
• Transistors can be biased in weak inversion.
• At weak inversion gm/Ids ratio is highest.

’’2.4-GHz Transceiver’’ ’’Measurement Results’’

• State of the art transceivers (250 KBit/S).

’’Measurement Results’’

• Measured Consumption Per Block

’’Measured Digital RX current consumption (PSDU = 20 bytes)’’

’’Die Photograph (130nm CMOS)’’

• 4mm2 Digital, 5mm2 Analog Circit area.

’’Picture of Demonstration Board’’ ”Summary”

• High-level system modeling.
• High-level system simulation.
• It is at the architectural level that most power is saved.
• Through high-level simulations that the impact of each.
• Minimizes complexity in Algorithms.

2009-08-27 23 Paper Presentation - Ultra Portable Devices

”Papers to Look into”

• W. Kluge et al., “A Fully Integrated 2.4-GHz IEEE802.15.4

Compliant Transceiver for ZigBeeTM Applications,” IEEE JSSC,Vol. 41, NO. 12, Dec. 2006, pp 2767-2775.

• H. Ishizaki, K. Nose, M. Mizuno, “A 2.4GHz ISM-band digital

wireless transceiver with an intra-symbol adaptively intermittent RX,” 2007 IEEE Symposium on VLSI Circuits Dig.

• Tech. Papers, pp. 84-85.