Outline Motivations High-tuning range VCO Synthesizer for - PDF document

Dottorato di Ricerca in Ingegneria Elettronica Informatica e delle Telecomunicazioni Short course on “RF electronics for wireless communication and remote sensing systems” Reconfigurable VCOs and Synthesizers Eleonora Franchi, Antonio Gnudi, Marco Guermandi DEIS-ARCES - University of Bologna Viale Risorgimento 2, Bologna, Italy Outline • Motivations • High-tuning range VCO • Synthesizer for reconfigurable transceivers • Measurement results • Conclusions

Motivations Frequency synthesis for multi-standard transceivers requires: � wide frequency range � versatility in channel spacing � high switching speed … all this with low phase-noise and low cost ! Available solutions � wide frequency range • VCO + dividers when possible (multiband) • switched tanks (L or C) or switched VCOs • technology boosters (bond-wire inductances or high C MAX / C MIN ratio capacitors) • VCOs + mixers for frequency shift (UWB) � versatility in channel spacing & switching speed • fractional-N PLL • reconfigurable loop-filter

Investigated solutions � wide frequency range • high-tuning range single-LC VCO • designed for 0.9-2.4 GHz continuous tuning � versatility in channel spacing & switching speed • fractional-N PLL with linearization and spurs cancellation techniques to break the bandwidth trade-off Main concept of high-tuning range VCO α γ 0.5 3 0.33 2 0.2 3/2 0.11 5/4 + α 1 = − α 1 γ

Problems with the previous concept α γ • For γ = 2 (1 FF) , α = 0.33 … too much for a common LC VCO 0.5 3 • For α = 0.2 (achievable for LC VCO), 0.33 2 γ = 3/2, but what about the duty cycle? 0.2 3/2 0.11 5/4 Fvco Ideal Fvco/(3/2) with 50% duty-cycle Realistic Fvco/(3/2) with duty-cycle not good for mixer More problems • For I/Q mo-demodulation, both in-phase and in- quadrature LO signals are required • A multiplexer is necessary for the selection of the output frequency sub-band A more effective solution is required !!

High-tuning range VCO: architecture 0.83-2.5 GHz 2.5-3.75 GHz (±20%) High-tuning range VCO: configuration A 0.83-1.25 GHz 2/3 Fvco 1/3 Fvco 1/3 Fvco Fvco

High-tuning range VCO: configuration B 1.25-1.87 GHz Fvco Fvco 1/2 Fvco DC High-tuning range VCO: configuration C 1.67-2.5 GHz 4/3 Fvco 1/3 Fvco 2/3 Fvco Fvco

Schematic of the core LC-QVCO • 5-bit capacitor ILO array for coarse tuning • amplitude control The quadrature is obtained by two Injection-Locked Oscillators (ILO) coupled by second harmonic Some theoretical results on the QVCO Stability of the solutions: “low swing” regime: I s1 I s2 in-phase V d1 V d2 in-phase “ high swing” regime: I s1 I s2 opp.-in-phase V d1 V d2 in-quadrature Quadrature oscillation is stable in the “high-swing” regime, that is also beneficial for low phase noise

QVCO explanation (1) Stable solution QVCO explanation (2) Stable solutions: depending on I s0 two possible regimes V S and I S opposite in phase: Quadrature obtained

More theoretical results on the QVCO Phase-noise analysis QVCO Single stage ILO r ω r R 1 r ω r R 1 θ = ⋅ ⋅ ⋅ 0 i θ = ⋅ ⋅ ⋅ 0 i n 1 nQ ω n 1 ω nQ V Q j 2 V 2 Q j 2 dm n dm n The QVCO and the single stage ILO have the same phase-noise x current product More theoretical results on the QVCO Sensitivity to tank mismatches     ω − ω 3 Q I 1     = ⋅ + ⋅ err s 0 01 02     ω 4 I 3     sm 0 The quadrature error is proportional to the ratio of the bias current over the coupling current and to the quality factor Q In the proposed scheme the output I/Q signals are generated by the DIV2 an extremely low I/Q error is NOT required from the QVCO

High tuning VCO: circuit design style • SCL logic for low sensitivity to parameter variations (differential style) • Adjustable bias current across the different sub-bands • Differential Gilbert cells for the SSB mixer. D-latch used in the MS-FF DIV2 Feedback path: DIV2 and MUX DIV2 Constant output Buffer

Schematic of the SSB mixer compensation for 50% duty-cycle Effect of the duty-cycle compensation Mixer outputs from simulations: w/o compensation with compensation

Chip micrograph STM 0.13 µm CMOS technology Summary of measured high-tuning range VCO performance Configuration A (1/3) B (1/2) C (2/3) Freq. range (GHz) 0.83 /1.25 1.25 /1.87 1.67 / 2.5 PN @ 1MHz (dBc/Hz) -130 / -126 -127.5 / -122.5 -126.5 / -120 LC-QVCO curr. (mA) 22.1 / 12.25 22.1 / 12.25 22.1 / 12.25 Reconf. curr. (mA) 5.3 8 9.5 Total current (mA) 27.5 / 17.6 30.1 / 20.2 31.5 / 21.7 Quadrature accuracy < 1° < 1° < 2°

Phase-noise measurements C (2 GHz) A (1 GHz) Meas. 0-3 GHz spectrum: configuration A

Meas. 0-3 GHz spectrum: configuration B Meas. 0-3 GHz spectrum: configuration C

Possible origin of the subharmonic spur in configuration C At the mixer output: fund. @ 4/3 Fvco + tone @ Fvco (1/3 Fvco offset) At the divider output: fund. @ 2/3 Fvco + tone @ 1/3 Fvco (same offset) Below -35 dBc in worst case over full frequency range Synthesizer for reconfigurable transceivers The classical integer-N architecture … high-tuning range VCO … is not adequate for channel spacing and switching speed

Σ∆ fractional-N synthesizer N/N+1 high-tuning range VCO b(t) = …001110101… Fractional-N obtained by varying the division ratio with a proper control sequence ( α = <b(t)>): F out = F ref x (N+ α ) Why fractional synthesis? • Easier trade off between reference frequency, loop bandwidth and output frequency resolution. – The reference frequency can be higher than channel spacing ⇒ Increase of the loop bandwidth. • Fine frequency step. – The frequency resolution can be much smaller than the reference (varying α =<b(t)> in very fine steps) • Multistandard receivers. – Reference frequency is independent on channel spacing

First order Σ∆ • Assuming a constant input: – The output mean is equal to the input – The quantization noise is high-pass shaped (see explanation on next slide) Noise shaping in first order Σ∆ General Σ∆ modulator Linear model with injected quantization noise Y ( z ) 1 1 = = N TF ( z ) = z First order: H ( z ) + E ( z ) 1 H ( z ) − 1 π f = N ( f ) 2 sin High-pass noise-shaping TF f s

Σ∆ of higher order and different type • Order = number of integrators (accumulators) • Higher order ⇒ Stronger noise shaping, Lower Spurs • Feedback type (single loop): critical stability. • MASH (Multi Stage noise Shaping): � Cascade of 1 st and/or 2 nd order Σ∆ . � Always stable. � Multibit output. Σ∆ Noise

Problems in fractional synthesis • PLL bandwidth still limited by Σ∆ quantization noise. • High sensitivity to PFD-CP linearity (in band noise leakage). • Actually sequences generated by Σ∆ are periodic: fractional spurs. Spur compensation concept (1) current injection related to the phase error at the input of the PFD, calculated by the control logic as M = 2 nbit   − K M x ( n ) ∆ φ = ∆ φ − + π ( n ) ( n 1 ) 2   x (n) = output + M N K   sequence

Spur compensation concept (2) 5+1 bits Quantization noise shaping also in the DAC current injection Multi-modulus divider Standard CMOS logic SCL logic prescaler (low-frequency part)

Linearization techniques… Typical linearity problems of the PFD-CP P-N gain dead-zone mismatch enhancement … in the PFD dead-zone suppression buffers to equalize loads Linearization techniques … in the CP Vbias = low-pass filtered version of V out Matching: size and bias

Alternative linearization technique: pulse injection Fixed number of VCO cycles In lock conditions the sunk current pulse forces the PFD-CP to work in the linear part of its characteristic. Circuit implementation • integrated in 0.13 µm CMOS STM technology … • … with the exception of the Σ∆ modulator, the control logic block of the compensation scheme and the largest capacitance of the loop filter • Σ∆ sequences are computed off-line and passed to the chip by a pattern generator • 70 MHz differential mode clock internally divided by two (35 MHz F ref ) • total area 1.8 x 2.0 mm 2

Measured settling time • 75 KHz measured 3-dB closed-loop bandwidth • 105 µs settling time Measured phase-noise plus spurs Conf. C 2.4 GHz output same integer ratio + fractional w/o comp. integer 2 dB decrease @ 10 MHz when division ratio compensation ON (not shown)

The amount of spur reduction depends on loop bandwidth 700 kHz BW 200 kHz BW curve A: integer N From former STM designs curve B: same N + fractional curve C: same N + fractional + spur compensation Effect of linearization techniques 15 dB 15 dB reduction of the in-band fractional spur when linearization is turned ON in the PFD-CP