Outline Outline Thermal Thermal- -Aware 3D IC Physical Design - PDF document

3D IC Design Tools and Applications to 3D IC Design Tools and Applications to Microarchitecture Exploration Microarchitecture Exploration Jason Cong Jason Cong UCLA Computer Science Department UCLA Computer Science Department cong@cs.ucla.edu cong@cs.ucla.edu http:// http://cadlab.cs.ucla.edu cadlab.cs.ucla.edu/~cong /~cong Outline Outline � Thermal Thermal- -Aware 3D IC Physical Design Flow Aware 3D IC Physical Design Flow � � Thermal Models and Assumptions Thermal Models and Assumptions � � 3D Routing with Thermal Via Planning � 3D Routing with Thermal Via Planning � 3D Placement � 3D Placement � 3D � 3D Floorplanning Floorplanning � 3D Architecture Exploration 3D Architecture Exploration � � 3D Component Modeling and Testing 3D Component Modeling and Testing � � Concluding Remarks and Future Work Concluding Remarks and Future Work � 2 Page

Thermal Challenges in 3 Thermal Challenges in 3- -D ICs D ICs Temperature distribution along z direction � Key Challenge of 3 Key Challenge of 3- -D IC D IC T � 150 o C Design: Design: 135 o C � Higher power density � Higher power density 100 o C � Inter Inter- -layer dielectric layer dielectric � layers layers � High Temperature High Temperature � 30 o C Effects: Effects: Z Si 1 � Longer interconnect Longer interconnect Si 2 � Si 3 Si 4 delays delays Temperature increases � Functional failure Functional failure � dramatically along the z direction 3 3 3- -D IC Cooling Schemes D IC Cooling Schemes � Heat Sink Optimization Heat Sink Optimization � � Air cooling fans Air cooling fans � � Heat radiating fins � Heat radiating fins � Thermal grease, AC, etc � Thermal grease, AC, etc .. .. � Chip Chip- -Level Temperature Level Temperature � Optimization Optimization � Microchannel � Microchannel cooling cooling � Floorplanning Floorplanning � � Routing Routing � � Thermal via insertion Thermal via insertion � 4 Page

Thermal Thermal- -Aware 3D Physical Design Flow at Aware 3D Physical Design Flow at UCLA (2002 – – 2005) 2005) UCLA (2002 Technology Design constraints Technology Netlist (LEFDEF) (LEFDEF) Design constraints Netlist Thermal- Thermal -Driven Driven 3D Floorplanner 3D Floorplanner Thermal Thermal Compact Thermal- Thermal -Driven Driven Compact Simulation Simulation Compact Open Open Thermal Thermal Open Thermal 3D Placement 3D Placement model model Access Access model Access Timing Timing Thermal- -Aware Aware Analysis Analysis Thermal 3D Router w/ 3D Router w/ Thermal Via Planning Thermal Via Planning Parasitic Parasitic Extraction Extraction CIF/GDSII CIF/GDSII Layout Layout Verification Verification 5 3D Physical Design Flow (IBM, UCLA, and PSU) 3D Physical Design Flow (IBM, UCLA, and PSU) (2006 (2006 – – present) present) Layer & Cell & Via* Netlist Design Rules definitions (HDL or DEF) (LEF) (LEF) PSU PSU UCLA UCLA Thermal Thermal- -Driven Driven 3D RC extraction 3D RC extraction 3D Floorplanner 3D Floorplanner 3D OA 3D OA Tech. Lib Tech. Lib Timing Timing Thermal- Thermal -Driven Driven EinsTimer EinsTimer Ref. Lib Ref. Lib 3D Placer 3D Placer Interface Interface Design Design 3D DRC & 3D LVS 3D DRC & 3D LVS 3D Global Router 3D Global Router Tier Tier Thermal Thermal- -Via Planner Via Planner Export Import Detailed Routing Detailed Routing Layout 2D OA 2D OA by Cadence Router by Cadence Router (GDSII ) 10/8/2007 UCLA VLSICAD LAB 6 Page

Thermal Resistive Network [Wilkerson04] Thermal Resistive Network [Wilkerson04] � Circuit stack partitioned into tiles P 5 5 R 5 � Tiles connected through P 4 4 thermal resistances R 4 P 3 3 � Lateral resistances: fixed R 3 P 2 2 � Vertical resistances ∝ 1/#via R 2 P 1 1 R 1 � Heat sources modeled as ± current sources - R lateral � Current value = power ( a) Tiles stack (b) Single tile array stack � Heat sinks modeled as ground nodes Accurate and slow 7 Thermal Resistive Chain Model Thermal Resistive Chain Model � One One- -Dimension Heat Flow Analysis Dimension Heat Flow Analysis � � � Elmore delay Elmore delay- -like formula [Chiang01] like formula [Chiang01] P 4 4 4 4 ∑ ∑ = T ( R P ) R 4 4 i j P 3 3 = = i 1 j i R 3 P 2 4 i 2 ∑ ∑ = T ( P R ) R 2 4 i j 1 P 1 = = i 1 j 1 R 1 ± � Reduce R: thermal via insertion (routing) - � Permute P: floorplanning Fast and rough 8 Page

Through Through- -the the- -Silicon Vias (TS Silicon Vias (TS- -Vias) in 3D ICs Vias) in 3D ICs Pad Metal Routing Block 1 Block 2 Layer Dielectric Through-the-Silicon Via Layer (Signal TS Via) Block 3 Through-the-Silicon Via (Thermal TS Via) Block 5 Block 4 Silicon (Device Layers) � Effective in heat dissipating Effective in heat dissipating � � Regular wires have almost no effect (size/direction) � Regular wires have almost no effect (size/direction) � Two types of TS Two types of TS- -vias vias � � Signal TS � Signal TS- -vias, part of the vias, part of the netlist netlist � Thermal TS � Thermal TS- -vias, with no connections, introduced to reduce vias, with no connections, introduced to reduce temperature temperature 9 Thermal- -Aware Aware 3D Routing Problem 3D Routing Problem Thermal � Input Input � � 3- -D floorplanning (placement) result D floorplanning (placement) result � 3 � � Technology Technology � � Netlist Netlist � Required temperature, such as 80 O O C C � Required temperature, such as 80 � Output Output � � � Routed nets Routed nets � � Thermal TS- Thermal TS -via number and locations via number and locations � Objectives Objectives � � Minimum wirelength � Minimum wirelength Minimum TS- -via number via number � � Minimum TS 10 Page

Multilevel TS- -Via Planning and 3D Routing (TMARS) Via Planning and 3D Routing (TMARS) Multilevel TS G 0 (1). Power Density Calculation Thermal Resistive G 0 Network Model (2). Heat Flow Estimation (3). Routing Resource Estimation G i level 0 level 0 G i (1) Routing Refinement (1). Power Density Coarsening (2). TTS Via Planning (2). Heat Flow Estimation (3). TTS Via Number Adjustment G k (3). Routing Resource Coarsening level i level i Upward Pass Downward Pass (1). Init Routing Tree Generation (2). TTS Via Planning (3). TTS Via Number Adjustment level k 11 Thermal TS- -Via Planning Problem Via Planning Problem Thermal TS Determines the thermal TS via density for all tiles Determines the thermal TS via density for all tiles � � Minimizing #total thermal TS via Minimizing #total thermal TS via � � Meeting capacity and temperature constraint Meeting capacity and temperature constraint � � Solving through Solving through � � � Via planning proportional to ∆ ∆ t t (VPPT) (VPPT) � Via planning proportional to • • ∆ ∆ t: vertical t difference t: vertical t difference � � Alternating direction via planning (ADVP) Alternating direction via planning (ADVP) 0 3 4 a 5 8 ∆ t a =t a -t b 1 6 2 5 b 0 10 8 12 Page

Thermal TS Via Planning [Cong & Zhang, ICCAD Thermal TS Via Planning [Cong & Zhang, ICCAD’ ’05] 05] Non- -Linear Programming Formulation Linear Programming Formulation Non � Variable Definition, for tile Variable Definition, for tile L L i, j, k � i, j, k � a i,j,k : TS-via number � R i,j,k : vertical thermal resistance � P i,j,k : current source � Ύ : constant R i,j,k = Ύ / a i,j,k � t i,j,k : temperature I i,j,k : heat flow � Objective Objective � γ N I ∑ ∑ t i,j,k = = i,j,k #total _ via a − i,j,k t t ≥ − � Constraints Constraints k 2 i,j,k i,j,k 1 � I i,j,k � Capacity constraint Capacity constraint � � Temperature constraint � Temperature constraint R i,j,k = Ύ /a i,j,k � Kirchoff's � Kirchoff's current law current law � Constrained NLP Constrained NLP � � Can be solved by general NLP solver Can be solved by general NLP solver � � But very time consuming But very time consuming � Fixed R ± 13 Alternating Direction TS Alternating Direction TS- -Via Planning (ADVP) Via Planning (ADVP) � Decompose the NLP into simplified sub Decompose the NLP into simplified sub- -problems problems � � Optimizing the via distribution at one direction at a time Optimizing the via distribution at one direction at a time � � � Alternating between vertical via planning and horizontal Alternating between vertical via planning and horizontal via planning at each level via planning at each level � Updating the heat flow after every step � Updating the heat flow after every step 14 Page