O N A C HIP S TACK WITH I NDUCTIVE C OUPLING T HROUGH C HIP I - - PowerPoint PPT Presentation

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O N A C HIP S TACK WITH I NDUCTIVE C OUPLING T HROUGH C HIP I - - PowerPoint PPT Presentation

Jan 02, 2024 277 likes •590 views

1 1 3D L AYOUT OF S PIDERGON , F LATTENED B UTTERFLY AND D RAGONFLY O N A C HIP S TACK WITH I NDUCTIVE C OUPLING T HROUGH C HIP I NTERFACE Hiroshi Nakahara , Ryota Yasudo , Hiroki Matsutani , Michihiro Koibuchi , Hideharu Amano

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3D LAYOUT OF SPIDERGON, FLATTENED BUTTERFLY AND DRAGONFLY ON A CHIP STACK WITH INDUCTIVE COUPLING THROUGH CHIP INTERFACE

Hiroshi Nakahara†, Ryota Yasudo†, Hiroki Matsutani†, Michihiro Koibuchi††, Hideharu Amano†

† Keio University, Japan †† National Institute of Technology, Japan

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BACKGROUND AND MOTIVATION

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Network-on-Chip

  • Network-on-Chip (NoC) is widely used.
  • The data are exchanged between routers as packets.
  • High degree of scalability compared with on-chip buses.

Chip is divided into tiles with a router

Tile Router 3 3

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  • Most of NoCs use 2D mesh topologies.
  • Routers can be connected with short links.
  • High clock frequency

However, the number of links between source and destination (hop count) becomes large.

  • Topologies with long links reduce hop count.
  • Spider

ergon, F , Flatten ened ed B Butter erfly, D , Dragonfly, etc. However, long links limit clock frequency.

Topologies of NoCs

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Example — Flattened Butterfly [1]

[1]. J. Kim, J. Balfour, and W.J. Dally, “Flattened butterfly topology for on-chip networks,” 40th Annual IEEE/ACM International Symposium on Microarchitecture, 2007. MICRO 2007., pp.172–182, Dec. 2007.

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loooooong link

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Our question

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Possible ?!

3D la D layout w with s h sma mall ll mu mult ltiple le c chi hips 2D la D layout w with s h sing ngle le la large c chi hip

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Our goal

  • Propose 3D layout with multiple chips

to reduce the maximum link length

  • In this paper, we study three existing

topologies

  • Spidergon, Flattened butterfly, Dragonfly

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3D CHIP STACKING TECHNOLOGY

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3D stacking technology

Two chips (face-to-face) Microbump Through silicon via Capacitive coupling Inductive coupling Wired Wireless Scalability Flexibility Three chips

  • r more

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Rx Rx Tx Tx Tx Tx Rx Rx Tx Tx Network k Int Interface TCI I

  • TCI

Network k Int Interface Accele lerator C Core Rx Rx Tx Tx Tx Tx Rx Rx Tx Tx CPU C U Core Rx Rx Tx Tx Tx Tx Network Int k Interface Da Data L Link nk Clo lock k Link nk Accelerator 1 Accelerator 2 Host CPU

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It consists of Receiver coils (Rx) and Transmitter coils (Tx).

ThroughChip Interface (TCI)

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Most wires are used for only testing and debugging 11 11

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TCI allows flexible structure

TX RX TX RX Layer 3 Layer 2 Layer 1 Layer 0 TX CLK RX TX RX Layer 3 Layer 2 Layer 1 Layer 0 RX TX TX TX

Example 1. Multiple chips in one layer Example 2. Links connecting distant chips

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⇔ Chips can horizontally

be shifted

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PROPOSED METHOD: 3D LAYOUT USING TCI

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Flattened butterfly topology [Kim et al., MICRO’08]

1-dimension Flattened butterfly 2-dimension Flattened butterfly 3-dimension Flattened butterfly

  • The topology depends on # of dimension.
  • The diameter is equal to # of dimension (quite low)

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We focus on this case.

・・・ ・・・ ・・・ ・・・

Low-diameter Scalable

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If we use a single chip… (2D layout)

  • The maximum link length becomes large.

… … … …

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Proposed method (3D layout)

  • Simply replace long links with vertical links.

Layer 3 Layer 2 Layer 1 Layer 0

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Each chip constitutes 2-dimension flattened butterfly. … … … … 2D layout

# of routers must be n3

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Dragonfly topology [Kim et al., ISCA’08]

  • High performance network for off-chip interconnection.
  • Already used in supercomputers listed in TOP500.

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Routers in a group constitutes a clique. All the groups constitute a clique.

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If we use a single chip… (2D layout)

  • Inter-group links becomes long.

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Example: 4 routers in a group

group

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Proposed method (3D layout)

  • All the inter-group links are replaced with vertical links.
  • The longest link is a inner-group link.
  • The maximum link length depends on the number of routers in a group.

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Layout on a chip (a group) Vertical links from Layer 0

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Spidergon topology

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Circle + normal lines # of nodes must be even.

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Spidergon can be represented as ladder-like structure

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≡

Two cross links are needed

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If we use a single chip… (2D layout)

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folding ‘ladder’

Cross links become longer as # of nodes increase

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Proposed method (3D layout)

  • Each chip has four nodes.
  • Use multiple chips in one layer.
  • so to speak, ‘ring-shaped ladder’

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# of routers can increase by 8. Cross links exist on a single chip!

Layer 0 Layer 1 Layer 2 Layer 3

.... ....

1 2 H-1 C0,0 CH-1,0 C1,0 C1,1 C2,0 C2,1 CH-2,0 CH-2,1

Multiple chips in one layer.

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RESULTS

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The maximum link length (Flattened butterfly)

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・ ・ ・

O(

3

√ N) O( √ N)

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The maximum link length (Dragonfly)

  • In our 3D layout, the maximum link length depends
  • n the number M of routers in a group.

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O( √ M) O( √ M)

O( √ N − √ M) O( √ N − √ M)

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The maximum link length (Spidergon)

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O(1) O( √ N)

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CONCLUSION

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Conclusion

  • 3D layout methods using TCI are proposed for the

following three topologies with long links.

  • Flattened butterfly
  • Dragonfly
  • Spidergon
  • Our methods reduce the maximum link length.
  • In particular, 3D layout of Spidergon has the constant

maximum length for any number of nodes.

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