CPSC 121 Models of Computation
Boolean logic Logic circuits
January 08, 2020 Patrice Belleville / Geoffrey Tien 1
Models of Computation Boolean logic Logic circuits January 08, - - PowerPoint PPT Presentation
CPSC 121 Models of Computation Boolean logic Logic circuits January 08, 2020 Patrice Belleville / Geoffrey Tien 1 Announcements Pre-lecture quiz #2 due Tuesday Jan.14, 19:00 Read Epp 4e/5e: Chapter 2.2 HW1 out soon, due Tuesday,
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AND 𝑌 𝑍 𝑎 F F F F T F T F F T T T OR 𝐵 𝐶 𝐷 F F F F T T T F T T T T NOT 𝐺 𝐻 F T T F 𝑎 = 𝑌 ∧ 𝑍 𝐷 = 𝐵 ∨ 𝐶 𝐻 = ~𝐺
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𝑏 𝑐 𝑑 𝑒 ? ? ? ? F F F F F F F T F F T F F F T T F T F F F T F T F T T F F T T T T F F F T F F T T F T F T F T T T T F F T T F T T T T F T T T T
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high low
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AND OR NOT, aka inverter
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AND OR NOT, aka inverter
XOR 𝑌 𝑍 𝑎 F F F F T T T F T T T F 𝑎 = 𝑌 ⊕ 𝑍
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The "bubble" means the value is inverted before entering the AND gate
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Note the inversions on the outputs of the OR and AND gates These are called NOR and NAND gates and are logically equivalent to inverting the OR/AND functions. Also note the 3-input AND function.
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