Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu MICRO-40, Chicago, December 2007
Parameter variation: roadblock to scaling Temperature Variation Process Variation Supply Voltage Variation 2 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Parameter variation: roadblock to scaling Temperature Variation Process Variation Within die (WID) Die-to-die (D2D) 2 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Parameter variation: roadblock to scaling 1.4 1 iation Proce Normalized Frequency Normalized Frequency 1.3 1.3 30% 1.2 1.2 130nm 1.1 1 Within die (WID 1.0 1 5X 0.9 0.9 1 2 3 4 5 1 2 3 4 5 Normalized Leakage (Isb Normalized Leakage ( Isb) ) [Shekhar Borkar, Intel Corp.] 2 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Technology scaling faces a major roadblock Temperature Variation Process Variation Threshold Voltage (V th ) Chip frequency Chip leakage power 3 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Body biasing • Well known technique for V th control • A voltage is applied between source/drain and substrate of a transistor • Forward body bias (FBB) V th Freq Leak • Reverse body bias (RBB) V th Freq Leak • Key knob to trade off frequency for leakage BB DVFS Leakage Dynamic Frequency Frequency power power 4 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Body bias design space Time Static Dynamic Space BB fixed for chip lifetime BB changes with T and workload D2D V th Variation D2D V th Variation Chip-wide T Variation [Intel Xscale] [Intel’s 80-core chip] WID V th Variation WID V th Variation Fine-grain T Variation (space and time) [Tschanz et al] 5 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Body bias design space Time Static Dynamic Space BB fixed for chip lifetime BB changes with T and workload D2D V th Variation D2D V th Variation Chip-wide T Variation [Intel Xscale] [Intel’s 80-core chip] WID V th Variation WID V th Variation S-FGBB D-FGBB Fine-grain n (space and time) [Tschanz et al] 5 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Outline • Background on S-FGBB • Dynamic fine-grain body biasing (D-FGBB) • Environments • Evaluation • Conclusions 6 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Outline • Background on S-FGBB • Dynamic fine-grain body biasing (D-FGBB) • Environments • Evaluation • Conclusions 7 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Static fine-grain body biasing [Tschanz et al, ISSCC 2002] V th variation Fine Grain Body Bias FBB RBB RBB RBB • The chip is divided in BB cells • Slow cells receive FBB - increase speed • Leaky cells receive RBB - save leakage • The result is reduced WID variation (delay, power) • BB voltages determined at manufacturing • Fixed for the lifetime of the chip 8 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Frequency binning Bin 1 High Bin 2 Frequency power Bin 3 Leakage power limit Bin 4 Leakage 9 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Frequency binning Bin 1 High Bin 2 Frequency power Bin 3 Leakage power limit Bin 4 Leakage 9 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Frequency binning Bin 1 High Bin 2 Frequency power Bin 3 Leakage power limit Bin 4 Leakage 9 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Frequency binning Bin 1 High Bin 2 Frequency power Bin 3 Leakage power limit Bin 4 Leakage 9 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Frequency binning Bin 1 High Bin 2 Frequency power Bin 3 Leakage power limit Bin 4 Leakage 9 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Calibration after manufacturing Calibration conditions (T cal , P max ) • Calibration takes place at maximum temperature T cal (burn-in oven) Frequency F orig Original Power chip limit Leakage 10 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Calibration after manufacturing Calibration conditions (T cal , P max ) • Calibration takes place at maximum temperature T cal (burn-in oven) Frequency P <P max F orig Original Power chip limit Leakage 10 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Calibration after manufacturing Calibration conditions (T cal , P max ) • Calibration takes place at maximum temperature T cal (burn-in oven) • F cal becomes the chip’s F cal P ≈ P max Frequency frequency F orig Original Power chip limit Leakage 10 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Outline • Background on S-FGBB • Dynamic fine-grain body biasing (D-FGBB) • Environments • Evaluation • Conclusions 11 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Motivation for D-FGBB • Significant temperature variation: • Space: across different functional units, on chip • Time: as the activity factor of the workload changes • Between average and worst case conditions (T cal ) • D-FGBB can exploit this temperature variation • Adapt the body bias to changing conditions 12 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Motivation for D-FGBB • Optimal body bias: The body bias than minimizes leakage power at the target frequency • Circuit delay changes with temperature • Therefore optimal BB changes with temperature The goal of D-FGBB is to keep the body bias optimal as T changes 13 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Finding the optimal BB • Measure the delay of each BB domain (cell) • Delay sampling circuit: FBB CLK Critical Path Phase Replica Detector RBB delay sampling circuit • Phase detector - measures delay of critical path replica • If slow - FBB signal raised • If fast - RBB signal raised 14 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Applying dynamic fine-grain BB • BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB Local Bias Generator DEC NMOS Vbb AND N-CNT D2A PMOS Vbb P-CNT D2A OR INC RBB FBB FBB RBB Body Bias Cell Body Bias Cell 15 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Applying dynamic fine-grain BB • BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB Local Bias Generator DEC NMOS Vbb AND N-CNT D2A PMOS Vbb P-CNT D2A OR INC RBB FBB FBB RBB Body Bias Cell Body Bias Cell 15 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Applying dynamic fine-grain BB • BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB Local Bias Generator DEC NMOS Vbb AND N-CNT D2A PMOS Vbb P-CNT D2A OR INC RBB FBB FBB RBB Body Bias Cell Body Bias Cell 15 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Applying dynamic fine-grain BB • BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB Local Bias Generator DEC NMOS Vbb AND N-CNT D2A PMOS Vbb P-CNT D2A OR INC RBB FBB FBB RBB Body Bias Cell Body Bias Cell 15 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Applying dynamic fine-grain BB • BB is determined based on feedback from delay samples Sample Points RBB FBB FBB RBB Local Bias Generator DEC NMOS Vbb AND N-CNT D2A PMOS Vbb P-CNT D2A OR INC RBB FBB FBB RBB Body Bias Cell Body Bias Cell • The BB changes until optimal delay is reached • BB stays constant, until T conditions change again 15 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Outline • Background on S-FGBB • Dynamic fine-grain body biasing (D-FGBB) • Environments • Evaluation • Conclusions 16 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
D-FGBB environments D-FGBB Operating environments Standard Minimize leakage power at F cal High performance Maximize average frequency Low Power Minimize leakage power at F orig 17 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
D-FGBB environments D-FGBB Operating environments Standard Minimize leakage power at F cal High performance Maximize average frequency Low Power Minimize leakage power at F orig 18 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Standard environment • S-FGBB finds Calibration conditions (T cal , P max ) and sets F cal F cal Frequency Original Power chip limit Leakage 19 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Standard environment • S-FGBB finds Calibration conditions (T cal , P max ) and sets F cal F cal Frequency Original Power chip limit Leakage 19 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Standard environment • S-FGBB finds Average conditions (T avg , P avg ) and sets F cal F cal Frequency S-FGBB at T avg Original Power chip limit Leakage 19 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
Standard environment • S-FGBB finds Average conditions (T avg , P avg ) and sets F cal D-FGBB at T avg F cal Frequency S-FGBB at T avg Original Power chip limit Leakage 19 Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007
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