Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing - - PowerPoint PPT Presentation

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Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing - - PowerPoint PPT Presentation

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Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu MICRO-40, Chicago, December 2007

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SLIDE 1

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas

MICRO-40, Chicago, December 2007

University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu

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SLIDE 2

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Parameter variation: roadblock to scaling

2

Temperature Variation Supply Voltage Variation Process Variation

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SLIDE 3

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Parameter variation: roadblock to scaling

2

Temperature Variation

Die-to-die (D2D)

Process Variation

Within die (WID)

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SLIDE 4

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Parameter variation: roadblock to scaling

2

iation Proce

Within die (WID

130nm

30% 5X

0.9 0.9 1 1.0 1 1.1 1.2 1.2 1.3 1.3 1 1.4 1 1 2 2 3 3 4 4 5 5 Normalized Leakage ( Normalized Leakage (Isb Isb) ) Normalized Frequency Normalized Frequency

[Shekhar Borkar, Intel Corp.]

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SLIDE 5

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Technology scaling faces a major roadblock

3

Process Variation Temperature Variation Threshold Voltage (Vth) Chip frequency Chip leakage power

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SLIDE 6

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Body biasing

4

  • Well known technique for Vth control
  • A voltage is applied between source/drain and

substrate of a transistor

  • Key knob to trade off frequency for leakage
  • Forward body bias (FBB)
  • Reverse body bias (RBB)

DVFS

Frequency Dynamic power

BB

Frequency Leakage power

Vth Freq Leak Vth Leak Freq

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SLIDE 7

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

WID Vth Variation [Tschanz et al] WID Vth Variation

Body bias design space

5

Static

BB fixed for chip lifetime

Dynamic

BB changes with T and workload

Chip-wide Fine-grain Space Time

D2D Vth Variation [Intel Xscale] [Intel’s 80-core chip] D2D Vth Variation T Variation T Variation (space and time)

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SLIDE 8

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

WID Vth Variation [Tschanz et al] WID Vth Variation

Body bias design space

5

S-FGBB Static

BB fixed for chip lifetime

Dynamic

BB changes with T and workload

Chip-wide Fine-grain Space Time

D2D Vth Variation [Intel Xscale] [Intel’s 80-core chip] D2D Vth Variation T Variation n (space and time)

D-FGBB

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SLIDE 9

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Outline

  • Background on S-FGBB
  • Dynamic fine-grain body biasing (D-FGBB)
  • Environments
  • Evaluation
  • Conclusions

6

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SLIDE 10

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Outline

  • Background on S-FGBB
  • Dynamic fine-grain body biasing (D-FGBB)
  • Environments
  • Evaluation
  • Conclusions

7

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SLIDE 11

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Static fine-grain body biasing

8

  • The chip is divided in BB cells
  • The result is reduced WID variation (delay, power)
  • Slow cells receive FBB - increase speed
  • Leaky cells receive RBB - save leakage

Vth variation Fine Grain Body Bias

FBB RBB RBB RBB

[Tschanz et al, ISSCC 2002]

  • BB voltages determined at manufacturing
  • Fixed for the lifetime of the chip
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SLIDE 12

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Bin 4 Bin 3 Bin 2 Bin 1

Leakage Frequency

Frequency binning

9

Leakage power limit High power

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SLIDE 13

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Bin 4 Bin 3 Bin 2 Bin 1

Leakage Frequency

Frequency binning

9

Leakage power limit High power

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SLIDE 14

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Bin 4 Bin 3 Bin 2 Bin 1

Leakage Frequency

Frequency binning

9

Leakage power limit High power

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SLIDE 15

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Bin 4 Bin 3 Bin 2 Bin 1

Leakage Frequency

Frequency binning

9

Leakage power limit High power

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SLIDE 16

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Bin 4 Bin 3 Bin 2 Bin 1

Leakage Frequency

Frequency binning

9

Leakage power limit High power

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SLIDE 17

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Calibration after manufacturing

10

Calibration conditions (Tcal, Pmax)

  • Calibration takes place at

maximum temperature Tcal

(burn-in oven)

Power limit Original chip Forig Frequency Leakage

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SLIDE 18

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Calibration after manufacturing

10

P <Pmax

Calibration conditions (Tcal, Pmax)

  • Calibration takes place at

maximum temperature Tcal

(burn-in oven)

Power limit Original chip Forig Frequency Leakage

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SLIDE 19

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal P ≈Pmax

Calibration after manufacturing

10

Calibration conditions (Tcal, Pmax)

  • Calibration takes place at

maximum temperature Tcal

(burn-in oven)

  • Fcal becomes the chip’s

frequency

Power limit Original chip Forig Frequency Leakage

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SLIDE 20

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Outline

  • Background on S-FGBB
  • Dynamic fine-grain body biasing (D-FGBB)
  • Environments
  • Evaluation
  • Conclusions

11

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SLIDE 21

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

  • D-FGBB can exploit this temperature variation
  • Adapt the body bias to changing conditions

Motivation for D-FGBB

  • Significant temperature variation:
  • Space: across different functional units, on chip
  • Time: as the activity factor of the workload changes
  • Between average and worst case conditions (Tcal)

12

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SLIDE 22

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

  • Optimal body bias:

The body bias than minimizes leakage power at the target frequency

13

  • Circuit delay changes with temperature
  • Therefore optimal BB changes with temperature

The goal of D-FGBB is to keep the body bias optimal as T changes

Motivation for D-FGBB

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SLIDE 23

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 delay sampling circuit

Finding the optimal BB

14

  • Measure the delay of each BB domain (cell)
  • Delay sampling circuit:
  • Phase detector - measures delay of critical path replica
  • If slow - FBB signal raised
  • If fast - RBB signal raised

Critical Path Replica Phase Detector FBB RBB

CLK

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SLIDE 24

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 15

Body Bias Cell Body Bias Cell Local Bias Generator N-CNT P-CNT D2A D2A

AND OR

DEC INC

RBB FBB RBB RBB RBB FBB FBB FBB

NMOS Vbb Sample Points PMOS Vbb

Applying dynamic fine-grain BB

  • BB is determined based on feedback from delay samples
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SLIDE 25

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 15

Body Bias Cell Body Bias Cell Local Bias Generator N-CNT P-CNT D2A D2A

AND OR

DEC INC

RBB FBB RBB RBB RBB FBB FBB FBB

NMOS Vbb Sample Points PMOS Vbb

Applying dynamic fine-grain BB

  • BB is determined based on feedback from delay samples
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SLIDE 26

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 15

Body Bias Cell Body Bias Cell Local Bias Generator N-CNT P-CNT D2A D2A

AND OR

DEC INC

RBB FBB RBB RBB RBB FBB FBB FBB

NMOS Vbb Sample Points PMOS Vbb

Applying dynamic fine-grain BB

  • BB is determined based on feedback from delay samples
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SLIDE 27

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 15

Body Bias Cell Body Bias Cell Local Bias Generator N-CNT P-CNT D2A D2A

AND OR

DEC INC

RBB FBB RBB RBB RBB FBB FBB FBB

NMOS Vbb Sample Points PMOS Vbb

Applying dynamic fine-grain BB

  • BB is determined based on feedback from delay samples
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SLIDE 28

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 15

Body Bias Cell Body Bias Cell Local Bias Generator N-CNT P-CNT D2A D2A

AND OR

DEC INC

RBB FBB RBB RBB RBB FBB FBB FBB

NMOS Vbb Sample Points PMOS Vbb

Applying dynamic fine-grain BB

  • The BB changes until optimal delay is reached
  • BB stays constant, until T conditions change again
  • BB is determined based on feedback from delay samples
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SLIDE 29

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Outline

  • Background on S-FGBB
  • Dynamic fine-grain body biasing (D-FGBB)
  • Environments
  • Evaluation
  • Conclusions

16

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SLIDE 30

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB environments

17

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

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SLIDE 31

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 18

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

D-FGBB environments

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SLIDE 32

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal

19

Power limit Original chip Frequency Leakage

Standard environment

  • S-FGBB finds

and sets Fcal

Calibration conditions (Tcal, Pmax)

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SLIDE 33

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal

19

Power limit Original chip Frequency Leakage

Standard environment

  • S-FGBB finds

and sets Fcal

Calibration conditions (Tcal, Pmax)

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SLIDE 34

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal

19

Power limit Original chip Frequency S-FGBB at Tavg Leakage

Standard environment

  • S-FGBB finds

and sets Fcal

Average conditions (Tavg, Pavg)

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SLIDE 35

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal

19

Power limit Original chip Frequency S-FGBB at Tavg Leakage

Standard environment

D-FGBB at Tavg

  • S-FGBB finds

and sets Fcal

Average conditions (Tavg, Pavg)

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SLIDE 36

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Fcal

19

Power limit Original chip Frequency S-FGBB at Tavg Leakage

Standard environment

D-FGBB at Tavg

  • S-FGBB finds

and sets Fcal

Average conditions (Tavg, Pavg) D-FGBB saves leakage power compared to S-FGBB at Fcal

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SLIDE 37

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

20

D-FGBB environments

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SLIDE 38

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

  • Average power

Pavg<<Pmax

21

Fcal Power limit Frequency Leakage

High performance

Calibration conditions (Tcal, Pmax)

Original chip S-FGBB at Tcal

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SLIDE 39

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

  • Average power

Pavg<<Pmax

21

Fcal Power limit Frequency S-FGBB at Tavg Leakage

High performance

Average conditions (Tavg, Pavg)

Original chip S-FGBB at Tcal

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SLIDE 40

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Favg D-FGBB

  • Average power

Pavg<<Pmax

21

Fcal Power limit Frequency S-FGBB at Tavg Leakage

High performance

Average conditions (Tavg, Pavg)

Original chip S-FGBB at Tcal

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SLIDE 41

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Favg D-FGBB

  • Average power

Pavg<<Pmax

21

Fcal Power limit Frequency S-FGBB at Tavg Leakage

High performance

Average conditions (Tavg, Pavg) D-FGBB improves average frequency

Original chip S-FGBB at Tcal

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SLIDE 42

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

22

D-FGBB environments

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SLIDE 43

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 23

Fcal Original chip Power limit Frequency Leakage

Low power

Average conditions (Tavg, Pavg)

Forig

  • The chip runs at its
  • riginal frequency (Forig)
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SLIDE 44

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 23

Fcal Power limit Frequency Leakage

Low power

Average conditions (Tavg, Pavg)

Forig S-FGBB D-FGBB

  • The chip runs at its
  • riginal frequency (Forig)
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SLIDE 45

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 23

Fcal Power limit Frequency Leakage

Low power

Average conditions (Tavg, Pavg)

Forig S-FGBB D-FGBB

  • The chip runs at its
  • riginal frequency (Forig)

D-FGBB saves leakage power at Forig

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SLIDE 46

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Outline

  • Background on S-FGBB
  • Dynamic fine-grain body biasing (D-FGBB)
  • Environments
  • Evaluation
  • Conclusions

24

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SLIDE 47

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Evaluation infrastructure

  • Process variation model - VARIUS [ASGI’07]
  • Generate Vth and Leff variation maps for 200 chips
  • SESC - cycle accurate microarchitectural simulator -

execution time, dynamic power

  • Mix of SPECint and SPECfp benchmarks
  • HotLeakage, SPICE model - leakage power
  • Hotspot - temperature estimation

25

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SLIDE 48

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Evaluation parameters

  • 4-core CMP

, based on Alpha 21364

  • 45nm technology, 4GHz
  • Vth variation: σVth/μVth=3-12%, σsys=σrand
  • Leff variation σLeff= σVth/2
  • Vdd=1V, Vth0=250mV, Vbb= ±500mV

26

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SLIDE 49

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

CMP architecture

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L2 Cache DCache Bpred FPReg FPAdd FPMul DTB ITB LdSTQ IntExec IntReg FPMap IntMap IntQ FPQ ICache

CMP

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SLIDE 50

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Body bias granularity

28

  • We evaluate FGBB at different granularities
  • 1 - 144 BB cells per chip
  • Shapes and sizes follow functional units

FGBB16 FGBB64 FGBB144

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SLIDE 51

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

29

D-FGBB environments

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SLIDE 52

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 30

Leakage Frequency

1.10 1.15 0.25 0.50 0.75 1.05 1.00 1

D-FGBB reduces leakage

D-FGBB1 D-FGBB16 D-FGBB64 D-FGBB144

  • More BB cells

result in higher frequency and lower leakage

NoBB

  • D-FGBB reduces

leakage significantly

28% 42% Leakage reduction

S-FGBB144 S-FGBB64 S-FGBB16 S-FGBB1

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SLIDE 53

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

31

D-FGBB environments

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SLIDE 54

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 32

Leakage Frequency

1.10 1.15 1 2 3 1.05 1.00 4

D-FGBB1 D-FGBB16 D-FGBB64 D-FGBB144

D-FGBB improves frequency

7%

  • More BB cells result

in a higher increase

NoBB S-FGBB1 S-FGBB16 S-FGBB64 S-FGBB144

9% Frequency increase

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SLIDE 55

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 32

Leakage Frequency

1.10 1.15 1 2 3 1.05 1.00 4

D-FGBB1 D-FGBB16 D-FGBB64 D-FGBB144

D-FGBB improves frequency

7%

  • More BB cells result

in a higher increase

2.5X

  • Significant power

cost, but still within the power budget

NoBB S-FGBB1 S-FGBB16 S-FGBB64 S-FGBB144

9% Frequency increase

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SLIDE 56

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

D-FGBB

Operating environments

Low Power

Minimize leakage power at Forig

Standard

Minimize leakage power at Fcal

High performance

Maximize average frequency

33

D-FGBB environments

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SLIDE 57

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007 34

Leakage Frequency

1.05 1.10 0.50 1.00 0.95 1

D-FGBB reduces leakage

10%

0.25 0.75

S1 S16 S64 S144 D1 D64 D144 D16 NoBB

  • More BB cells result

in higher savings

51% Leakage reduction

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SLIDE 58

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

Conclusions

  • D-FGBB is more effective than S-FGBB at reducing

WID variation:

35

D-FGBB

Frequency Leakage power

  • D-FGBB can give architects an additional knob to

tradeoff frequency/power

  • because D-FGBB adapts to T variation
  • 50% lower leakage
  • 10% higher frequency
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SLIDE 59

Radu Teodorescu, UIUC MICRO-40, Chicago, December 2007

More in the paper...

  • Details about our variation model
  • A solution for combining D-FGBB with DVFS
  • Estimated overheads of D-FGBB
  • More implementation details

36

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SLIDE 60

Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing

Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep Torrellas

MICRO-40, Chicago, December 2007

University of Illinois at Urbana-Champaign http://iacoma.cs.uiuc.edu