Microarchitectural Attacks in the Cloud
Thomas Eisenbarth 07.11.2017
Workshop on Cryptography for the Internet of Things and Cloud Ruhr-Universität Bochum
Microarchitectural Attacks in the Cloud Thomas Eisenbarth - - PowerPoint PPT Presentation
Microarchitectural Attacks in the Cloud Thomas Eisenbarth 07.11.2017 Workshop on Cryptography for the Internet of Things and Cloud Ruhr-Universitt Bochum Outline Cloud and Cryptography Co-Location in the Cloud Cache Attacks in the
Thomas Eisenbarth 07.11.2017
Workshop on Cryptography for the Internet of Things and Cloud Ruhr-Universität Bochum
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– Attacks only via intended interfaces – Side Channels are minor concern – Fine-grain timing over network is difficult – If attacker monitors your CPU, bad crypto implementation is not your main problem
– No worries, your data is secure
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Modern CPUs microarchitecture: “Make the common case fast”
Order Execution
processor System & Support
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located VMs cost savings
VMs.
➢Hardware leakages are still poorly protected, malicious VMs can still cause lots of damage.
Hardware VMM
Guest OS #1 Guest OS #2
VM VM
Spy Victim
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the victims process (Cross core & cross CPU)
bit flips that can break isolation across VMs
keys, passwords..
Guest OS #1 Guest OS #2
VM VM
Spy Victim
Shared L3 CACHE
Guest OS #1 Guest OS #2
VM VM
Spy Victim
DRAM
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First success in 2009 on AWS [RTS09]:
– Logical Side Channels: Ping time, IP address of instance or hypervisor? – Arch. Side Channels: Disk Load?
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* In Sept 2008
[RTSS09] Ristenpart, T., Tromer, E., Shacham, H., and Savage, S. Hey, You, Get off of My Cloud: Exploring Information Leakage in Third- party Compute Clouds. ACM CCS '09
AWS EC2:
– Ping is constant time – HDDs replaced with SSDs – Dom0 IPs hidden – Logical side channels are closed
➢New Co-location detection needed
– Cache Covert Channel – Software Profiling in LLC – Memory Bus Locking
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Architectural Side Channels difficult to prevent
[XWW15] XU, Z., WANG, H., AND WU, Z. A measurement study on co-residence threat inside the cloud. USENIX Security 15 [VZRS15] VARADARAJAN, ZHANG, RISTENPART, AND SWIFT: A placement vulnerability study in multi-tenant public clouds. USENIX Security 15 [IGES16] Inci, Gulmezoglu, Eisenbarth, Sunar: Co-location Detection on the Cloud COSADE 16
Line n Line n+1
coherency and synchronization
– CMPXCHG, FADDL, XADDL etc.
– The cache line is locked
locking single cache line not sufficient
– From pipelines of all cores and CPUs – Works in multi-socket systems
penalty to other applications
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data data
Microachitectural Attacks in the Cloud - Thomas Eisenbarth
Azure IaaS: 2nd largest IaaS, fastest growing Cloud?
Use bus locking (µArch channel) as ground truth to identify logical channelscheaper, faster, stealthy
– 4 different accounts: East US2 region – 20 single/dual VMs per account – 0.75GB RAM; Ubuntu 14.04 – Azure command line interface
➢ 120 co-located pairs
➢Private IPs: 60 machines per subnet ➢All co-located machines in same /16 subnet
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Co-resident VMs reside in same subnets + share MAC vID
Co-residency
– If internal port open: retrieve service (e.g. HTTP) directly – If internal port closed: scan external IP specifying the MAC address If the VM is co-resident and MAC address matches response; else no response
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[IIES16] Inci, Irazoqui, Eisenbarth, Sunar: Efficient, Adversarial Neighbor Discovery using Logical Channels on Microsoft Azure ACSAC 2016
detection
– cheap, fast, stealthy, but preventable by ISP
– difficult to prevent remain open – harder to exploit
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(70x slowdown)
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– Kernel Same page Merging in Linux and KVM – Transparent Page Sharing in VMware VMM – Solutions for Xen available as well Is now an opt-in feature for VMMs! (Default for OSs)
– page copied to cache: copy in shared LLC – Subsequent Spy VM access also faster! Spy can detect Target VMs accesses to known pages
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Source:
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Private L1/L2 CACHE Shared L3 CACHE Memory Victim Spy
Fast reload time Slow reload time
Clean detection if monitored memory line was accessed
Steps:
Detect key-dependent cache accesses:
– Sliding window exponentiation – Occurrence of multiplicands in cache reveals key bits
– T-table implementation: Xors and table lookups – Detect t-table access in last round (table entry corresponding to 𝑑𝑗is always in LLC)
19 [YF14] Y Yarom, KE Falkner Flush+ Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack, USENIX Security 2014 [IIES14] Irazoqui, G., Inci, M. S., Eisenbarth, T., & Sunar, B. Wait a minute! A fast, Cross-VM attack on AES. RAID 2014 Microachitectural Attacks in the Cloud - Thomas Eisenbarth
Cross-VM Flush+Reload Attacks work if
located
cache attacks
– http://kb.vmware.com/kb/2080735
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1. Flush Prime memory lines
fill monitored cache set with dummy data: eviction set
3. Reload Probe memory lines
read eviction set data and time read
– Usually only applied on L1-cache (64kb) not cross-core – L3-Cache is too large(25MB!) and not controllable? Solution: Huge Pages give control of L3$ to spy
22 [Hu92] Hu, W.-M. (Digital Equipment Corp., Littleton, MA, USA) Lattice scheduling and covert channels. IEEE Oakland 92 [OST06] DA Osvik, A Shamir, E Tromer Cache attacks and countermeasures: the case of AES. CT-RSA 2006 Microachitectural Attacks in the Cloud - Thomas Eisenbarth
Cross-VM Cache Attacks on crypto such as El Gamal [LY+15] or AES [IES15] work if
located
23 [LY+15] Liu, F., Yarom, Y., Ge, Q., Heiser, G., & Lee, R. B. (2015). Last-Level Cache Side-Channel Attacks are Practical. (S&P 2015). [IES15] Irazoqui, G., Eisenbarth, T., & Sunar, B. S$A: A shared cache attack that works across cores and defies VM sandboxing—and Its application to AES. 36th IEEE Symposium on Security and Privacy (S&P 2015) Microachitectural Attacks in the Cloud - Thomas Eisenbarth
– Intel Xeon E5 2670 v2 CPU @2.5 GHz – 10 cores share 25 MB of L3 cache – Modified (Hardened) Xen VMM – Up to 10 co-located instances (VMs)
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(no within-acc colocation)
relevant targets
Microachitectural Attacks in the Cloud - Thomas Eisenbarth
– Co-location via LLC channel
– AES key extraction with ciphertext – Code-Detection: e.g. crypto libraries
(openSSL/Libgcrypt) are widely patched
– Targets of opportunity instead of targeted attacks?
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Case study: EC2 South America East region
Alternate Approach: Bulk Key Recovery
Recover many keys at once
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Scenario:
Suite
combined with FFT
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[GES17] B. Gulmezoglu and T. Eisenbarth and B. Sunar: Cache-Based Application Detection in the Cloud Using Machine Learning AsiaCCS 2017
Native L1
➢Up to 97.95% SR
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LLC: Native vs. AWS
➢77.65% SR in Native ➢60.22% in EC2 Cloud
Microachitectural Attacks in the Cloud - Thomas Eisenbarth
private browsing?
– 10k to 50k events on 3 counters – Convolutional Neural Networks and SVMs perform best
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Up to 86% on Google Chrome (private mode) Up to 71% on Tor Browser
Microachitectural Attacks in the Cloud - Thomas Eisenbarth
[GZES17] B.Gulmezoglu and A. Zankl and T. Eisenbarth. and B. Sunar PerfWeb: How to Violate Web Privacy with Hardware Performance Events ESORICS 2017
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Requirements:
Simple Mitigations:
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up to 70x execution time prevents many attacks protects L1 & L2 caches for security-critical apps Attacker can build replacements
Microachitectural Attacks in the Cloud - Thomas Eisenbarth
Idea: Don’t share cache
➢Performance degradation from small cache Examples:
– software-only approach
– uses Intel’s Cache Allocation Technology (CAT)
35 [KPM12] KIM, PEINADO, MAINAR-RUIZ: STEALTHMEM: system-level protection against cache-based side channel attacks in the cloud. USENIX Security 12 [LGY+16] LIU, GE, YAROM, et al.: Catalyst: Defeating last-level cache side channel attacks in cloud computing IEEE HPCA 2016 Microachitectural Attacks in the Cloud - Thomas Eisenbarth
Write unexploitable Code
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possible
– SGX is not going to change that
– CSPs can hinder – Dedicated server for security-critical tasks
– Design philosophy better than patchwork of fixes
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vernam.wpi.edu its.uni-luebeck.de thomas.eisenbarth@uni-luebeck.de
Microachitectural Attacks in the Cloud - Thomas Eisenbarth