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Chip Multiprocessor
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Memory Access Latency Joshua San Miguel Natalie Enright Jerger - - PowerPoint PPT Presentation
Memory Access Latency Joshua San Miguel Natalie Enright Jerger - - PowerPoint PPT Presentation
Load Value Approximation: Approaching the Ideal Memory Access Latency Joshua San Miguel Natalie Enright Jerger Chip Multiprocessor main memory shared caches, network-on-chip private cache miss private cache private cache core core core
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Approximate Data
Many applications can tolerate inexact data values.
- In approximate computing applications, 40% to nearly 100% of
memory data footprint can be approximated [Sampson, MICRO 2013].
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Approximate data storage:
- Reducing SRAM power by lowering supply voltage [Flautner, ISCA 2002].
- Reducing DRAM power by lowering refresh rate [Liu, ASPLOS 2011].
- Improving PCM performance and lifetime by lowering write precision and
reusing failed cells [Sampson, MICRO 2013].
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Outline
- Load Value Approximation
- Approximator Design
- Evaluation
- Conclusion
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator miss A
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator generate A_approx
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator A_approx
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator A_approx request A_actual
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator A_approx train with A_actual
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Load Value Approximation
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core core core private cache private cache private cache shared caches, network-on-chip main memory approximator approximator approximator
Takes memory access off critical path.
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Approximator Design
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ℎ , 1.0 2.2 3.1
instruction address
global history buffer
tag tag tag tag tag tag tag tag
approximator table
𝑔
local history buffer
4.1 3.9 4.0
PC ⊕ 1.0 ⊕ 2.2 ⊕ 3.1 (4.1 + 3.9 + 4.0) / 3 A_approx = 4.0 load A
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Approximator Design
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Load value approximators overcome the challenges of traditional value predictors:
- No complexity of tracking speculative values.
- No rollbacks.
- High accuracy/coverage with floating-point values.
- More tolerant to value delay.
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Evaluation
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EnerJ framework [Sampson, PLDI 2011]:
- Program annotations to distinguish approximate data from
precise data.
- Evaluate final output error and approximator coverage.
benchmark GHB size LHB size approximator size fft 2 49 kB lu 3 1 32 kB raytracer 1 1 32 kB smm 5 1 32 kB sor 2 49 kB
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Evaluation
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0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% fft lu raytracer smm sor
- utput error
approximator coverage
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Conclusion
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Future work:
- Further explore approximator design space (dynamic/hybrid
schemes, machine learning).
- Measure speedup of load value approximation using full-
system simulations.
- Measure power savings (low-power caches/NoCs/memory for
approximate data).
Low-error, high-coverage approximators allow us to approach the ideal memory access latency.
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Thank you
18 baseline (precise) - raytracer load value approximation - raytracer