LRR-DPUF: Learning Resilient and Reliable Digital Physical - - PowerPoint PPT Presentation

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LRR-DPUF: Learning Resilient and Reliable Digital Physical - - PowerPoint PPT Presentation

Feb 14, 2024 126 likes •401 views

LRR-DPUF: Learning Resilient and Reliable Digital Physical Unclonable Function Jin Miao 1 Meng Li 2 Subhendu Roy 1 Bei Yu 3 1 Cadence Design Systems 2 University of Texas at Austin 3 The Chinese University of Hong Kong 1 / 26 Outline

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SLIDE 1

LRR-DPUF: Learning Resilient and Reliable Digital Physical Unclonable Function

Jin Miao1 Meng Li2 Subhendu Roy1 Bei Yu3

1Cadence Design Systems 2University of Texas at Austin 3The Chinese University of Hong Kong

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SLIDE 2

Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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SLIDE 3

Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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SLIDE 4

Introduction

Conventional analog silicon PUFs

◮ Transistor analog intrinsic randomness ◮ Vulnerable to environmental and operational variations ◮ Need error correction

Expected digital silicon PUF

◮ Boolean type randomness source ◮ Immune to environmental and operational variations ◮ Less to no error correction ◮ Strong resilience to attacks

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SLIDE 5

Introduction

Related work

◮ Hybrid FPGA digital PUF however need analog PUF to start up [FPL

’14]

◮ First digital PUF by interconnection uncertainty yet only conceptual and

less feasible for practice [ISQED’15]

Contributions in our work

◮ Quantitative justifications of the use of interconnect randomness ◮ Strongly skewed latches to ensure deterministic transistor behaviors ◮ Novel highly non-linear logic network to ensure strong security

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SLIDE 6

Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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SLIDE 7

Lithography variations

Identify a feasible source of Boolean randomness is half the battle to make a digital PUF.

Two slightly differed mask stripe-pairs are eventually mapped to have different connectivities on silicon.

3nm 5nm Interconnect under lithography variation. Left: mask split of 20nm for top, 28nm for bottom. Right: shapes on wafer.

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SLIDE 8

Lithography variations

Lithography variation categories

◮ Systematic: dose, focus, etc. ◮ Local: mask, line edge roughness (LER), etc.

Mask error for interconnect randomness

◮ Position two interconnect layout line-ends close to each other ◮ An electron beam system can easily lead to large mask variations ◮ Mask variation further maps to different connectivity in wafer

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Lithography variations

Quantitative justifications of lithography variations

◮ The existence and control of the configurations to

◮ Augment the local variation ◮ Suppress the systematic variation

0.4 0.5 0.6 0.7 0.8 0.9 1 35 40 45 50 selected mean Connectivity Rate Layout Split Distance (nm) 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05 1 2 3 4 5 selected stdv. Connectivity Rate Mask Error Stdv. Distance (nm) 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 0.98 0.99 1 1.01 1.02 Connectivity Rate Dose Value (normalized)

Interconnect connectivity rate under lithography variations: Left: layout split distance under mask error stdv. of 4nm; Center: mask error stdv. under split of 46nm; Right: dose values.

Conclusion

Lithography variations can be utilized by careful configurations of layout split and E-beam accuracy.

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SLIDE 10

Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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Unit Cell

Naïve random interconnection is incompatible to digital CMOS.

◮ Short-circuit: direct current from Vdd to Gnd, uncertain region, etc. ◮ Open-circuit: floating gate, etc.

Goal: Pure logical circuit compatible for normal and open circuits

Strongly skewed latch!

A B

skew-1 skew-0

0.2 0.4 0.6 0.8 1 0.2 0.4 0.6 0.8 1 VB (V) VA (V) skewed-1 inv skewed-0 inv

Handling dangled poly-gate by strongly skewed latch. Left: inverter pair based skewed latch; Right: the VTC relation of a strongly skewed latch.

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Unit Cell

Exclusive-OR (XOR) cell property

◮ Linear non-separable

(a) (b) A B C 1 1 1

response is 0 response is 1

A B 1 1

Linear non-separable nature for XOR logic. ◮ Equal output probability

If Pr[a = 1] = Pr[a = 0] = 0.5, ∀b ∈ B, then Pr[y = 1] = Pr[y = 0] = 0.5.

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SLIDE 13

Unit Cell

The proposed unit cell

virtual connection key

  • utput

key

  • utput

virtual connection skew-1 skew-0

Left: the complete unit cell logic structure; Right: simplified symbolic representation.

A unit cell may or may not invert its key depending on virtual connection.

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SLIDE 14

Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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SLIDE 15

LRR-DPUF architecture

The proposed LRR-DPUF architecture

Z Z Z Z Z Z … … … … … … … … … … … … … … … … … … … … … … … … N rows M colums in0 in1 in2 in3 in4 inN-1

  • ut0
  • ut1
  • ut2
  • ut3
  • ut4
  • utN-1

… …

A N-row by M-col LRR-DPUF architecture. Some boundary virtual connections are marked by “Z” indicating dangling status.

Each row is a signal tunnel where the 1-bit input signal may be inverted depending on the virtual connections associated to this row.

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LRR-DPUF architecture

LRR-DPUF formula

ki,j =          ki,j−1 ⊕ (v · ki+1,j−1 + v), i even, j even; ki,j−1 ⊕ (v · ki−1,j−1 + v), i even, j odd; ki,j−1 ⊕ (v · ki−1,j + v), i odd, j even; ki,j−1 ⊕ (v · ki+1,j + v), i odd, j odd.

Here ki,j refers to i-row j-column output, and v refers to virtual connection status.

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SLIDE 17

LRR-DPUF architecture

Logic cone of an 8×8 LRR-DPUF

Z Z Z Z Z Z

  • ut0

Z Z

  • ut1
  • ut2
  • ut3
  • ut4
  • ut5
  • ut6
  • ut7

in0 in1 in2 in3 in4 in5 in6 in7

Logic cone of out2 is highlighted in red color.

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LRR-DPUF architecture

LRR-DPUF properties

◮ The non-linearity of LRR-DPUF increases along with a higher connectivity rate. ◮ There is a sufficiently large space of unique LRR-DPUFs even if the connectivity

rate is high.

◮ Increasing the number of columns strengthens the resilience to learning attacks. ◮ Any subtle change on virtual connections will be reflected to multiple outputs.

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Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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Evaluation

Statistical evaluation

Table: Statistical evaluation on 8 × 8 LRR-DPUF with 256 exhaustive CRPs

Type (Ideal Value)

  • conn. rate = 0.2
  • conn. rate = 0.9

Mean Stdv. Mean Stdv. Inter HD (0.5) 0.4188 0.0302 0.4943 0.0061 Intra HD (0.0) Bit Alias (0.5) 0.5000 0.2067 0.5000 0.0730 Uniformity (0.5) 0.5000 0.1768 0.5000 0.1678

Table: Statistical evaluation on 64 × 64 LRR-DPUF with 100K CRPs

Type (Ideal Value)

  • conn. rate = 0.2
  • conn. rate = 0.9

Mean Stdv. Mean Stdv. Inter HD (0.5) 0.4999 0.0009 0.5000 0.0009 Intra HD (0.0) Bit Alias (0.5) 0.5000 0.0504 0.5000 0.0499 Uniformity (0.5) 0.5000 0.0625 0.5000 0.0624

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Evaluation

Avalanche effect

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 Impacted Output # ith Input Bit

  • con. ratio = 0.9
  • con. ratio = 0.2

Avalanche effect of 8×8 LRR-DPUF over each input.

Under high connectivity rate, the adversary prediction via one bit change at a time is no better than a simple random guess.

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Evaluation

Adversary attacks: 8-row by various number of columns

10% 15% 20% 25% 30% 35% 40% 45% 50% 55% 0% 20% 40% 60% 80% 100% Prediction Error Training Set Ratio 8-row, 128-col 8-row, 32-col 8-row, 16-col 8-row, 8-col 20% 25% 30% 35% 40% 45% 50% 55% 60% 0% 20% 40% 60% 80% 100% Prediction Error Training Set Ratio 8-row, 128-col 8-row, 32-col 8-row, 16-col 8-row, 8-col

SVM attack for 8-row LRR-DPUFs over different configurations: Left: connectivity rate of 0.2 over different column sizes and training sizes; Right: connectivity rate of 0.9 over different column sizes and training sizes;

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Evaluation

Adversary attacks: 64-row by 64-colum

0% 10% 20% 30% 40% 50% 60% 70% 80% 0% 20% 40% 60% 80% 100% Prediction Error Training Set Ratio

  • con. ratio = 90%
  • con. ratio = 20%
  • con. ratio = 10%
  • con. ratio = 1%

46% 48% 50% 52% 54% 0% 20% 40% 60% 80% 100% Prediction Error Training Set Ratio RF w/ con. ratio = 90% RF w/ con. ratio = 20% ANN w/ con. ratio = 90% ANN w/ con. ratio = 20%

Left: SVM attacks over different connectivity rate and training size. Right: additional learning model attacks including i) Artificial neural network (ANN) with 10 hidden layers using Sigmoid function, and ii) Random Forest (RF) with 15 trees in the forest.

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Outline

Introduction Lithography variation Unit Cell LRR-DPUF architecture Evaluation Conclusion

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Conclusion

◮ A novel learning resilient and reliable digital PUF ◮ Justification for the use of interconnect randomness ◮ Strongly skewed latches for CMOS compatibility ◮ A highly non-linear logic architecture

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Thank You

Jin Miao (jmiao@cadence.com) Meng Li (meng_li@utexas.edu) Subhendu Roy (subhroy@cadence.com) Bei Yu (byu@cse.cuhk.edu.hk)

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