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Lets port together. Debian fun for everyone. Lets port together. Debian fun for everyone. Peter De Schrijver Most civilised people are out of touch with reality because Outline they confuse the world as it is with the world as they

SLIDE 1

Let’s port together. Debian fun for everyone. Peter De Schrijver Outline

Let’s port together. Debian fun for everyone.

”Most civilised people are out of touch with reality because they confuse the world as it is with the world as they think about it, talk about it and describe it.” Peter De Schrijver p2@debian.org February 24, 2007

SLIDE 2

Let’s port together. Debian fun for everyone. Peter De Schrijver Outline

Overview I

Portability issues why ? C types Bitfields Endianness Alignment Accesing peripheral hardware Example system architectures Trends in system design Out of order transactions Non-coherent I/O Userland hardware access

SLIDE 3

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Why ?

◮ Correctness ◮ Debian is ”The Universal Operating System” ◮ Debian is the most used Embedded Distribution ◮ Hardware advances will make Debian feasible on new

platforms

◮ It’s enlightening to see and play with other

architectures/systems

SLIDE 4

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

C types

◮ ANSI-C

◮ sizeof(char) <= sizeof(short) <= sizeof(int) <=

sizeof(long)

◮ short and int are at least 16bit ◮ long is at least 32bit ◮ sizeof(ptr) ! = sizeof(int) ◮ signedness of chars is arch dependent

◮ Tips

◮ use int as much as possible for computations, loop

variables,...

◮ use ISO C99 types (u int8, u int16, u int32, ...) for

external comms

◮ don’t abuse chars to ’save memory’ ◮ use the latest gcc version with -Wall

SLIDE 5

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Bitfields

typedef struct bitfields { unsigned char bitfield0:3; unsigned char bitfield1:5; } IA32 representation :

7 6 5 4 3 2 1

PowerPC representation :

1 2 3 4 5 6 7

SLIDE 6

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Endianness

Consider 0x12345678 Little endian : 0x78 0x56 0x34 0x12 Big endian : 0x12 0x34 0x56 0x78 PDP endian : 0x34 0x12 0x78 0x56

◮ External interfaces ◮ Use macros to convert between CPU and specific

endianess

SLIDE 7

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Alignment

◮ Most RISC cpus require aligned accesses ◮ Unaligned accesses are trapped (mostly)

◮ slow ◮ not possible in kernel land

◮ Unaligned accesses are seldomly atomic with respect to

SMP/other bus masters

◮ Better

◮ avoid them ◮ have the compiler generate the code

SLIDE 8

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Intel style system

CPU CPU North bridge Memory subsystem Device Device Device

SLIDE 9

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Intel style system

◮ Main components

◮ CPU complex ◮ Northbridge ◮ Southbridge ◮ Memory subsystem

◮ Main interfaces

◮ Frontside bus ◮ PCI ◮ AGP

SLIDE 10

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Opteron style system

CPU CPU HT PCIe bridge Memory subsystem Device Device Device Memory subsystem HT PCIe bridge Device Device Device

SLIDE 11

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Opteron style system

◮ Main components

◮ CPU ◮ Hypertransport - PCIe bridge ◮ PCIe - PCI bridge

◮ Main interfaces

◮ Hypertransport ◮ PCIe ◮ PCI

SLIDE 12

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Trends in system design

◮ Observations

◮ CPUs became much faster then memory ◮ bus and memory bandwidth have gone up faster then

latencies

◮ parallel busses become very hard at high speeds

◮ Solutions

◮ Caches ◮ Burstmode transfers ◮ Advanced DMA ◮ multiple highspeed serial links

SLIDE 13

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Out of order transactions

◮ examples

◮ CPU ◮ bus bridges

◮ use read/write barriers

◮ CPU instructions ◮ ”magic” reads

possibly out of order : stw r20,0x20(r21) stw r22,0x24(r21) always in order : stw r20,0x20(r21) eieio stw r22,0x24(r21)

SLIDE 14

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Non-coherent I/O

◮ Some systems do not support ”bus snooping” ◮ Invalidate cachelines

◮ network traffic ◮ disk buffers ◮ other kinds of streaming I/O

◮ non-cacheable memory

◮ microcode ◮ ring buffers

SLIDE 15

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Addressing

◮ Virtual addresses ◮ Physical addresses ◮ Bus addresses ◮ Translation Physical to Bus addresses

◮ identity mapped ◮ fixed offset ◮ page based translation ◮ not memory mapped ◮ IA32 I/O ports ◮ PowerPC DCB

◮ Always access hardware via special functions

SLIDE 16

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Transaction atomicity

◮ Multiple CPUs ◮ other busmasters (eg. on PCI) ◮ reads and writes are atomic only if aligned ◮ atomic read/modify/write is CPU specific

◮ ia32: lock prefix on specific instructions ◮ mips: ll/sc ◮ arm: swap ◮ ppc: lwarx/stwcx

◮ bridges may break locks

SLIDE 17

Let’s port together. Debian fun for everyone. Peter De Schrijver Portability

Why ? C types Bitfields Endianness Alignment

Peripherals

Architectures Trends Out of order I/O Userland

Userland hardware access

◮ Hardware access from userland is problematic ◮ Seperate command transport from driver logic

◮ Firewire : libraw1394 ◮ USB : libusb ◮ SCSI and ATAPI : scsi generic like ioctl ◮ ...

Let’s port together. Debian fun for everyone.

”Most civilised people are out of touch with reality because they confuse the world as it is with the world as they think about it, talk about it and describe it.” Peter De Schrijver p2@debian.org February 24, 2007

Overview I

Portability issues why ? C types Bitfields Endianness Alignment Accesing peripheral hardware Example system architectures Trends in system design Out of order transactions Non-coherent I/O Userland hardware access

Why ?

◮ Correctness ◮ Debian is ”The Universal Operating System” ◮ Debian is the most used Embedded Distribution ◮ Hardware advances will make Debian feasible on new

platforms

◮ It’s enlightening to see and play with other

architectures/systems

C types

◮ ANSI-C

sizeof(long)

◮ Tips

variables,...

external comms

Bitfields

typedef struct bitfields { unsigned char bitfield0:3; unsigned char bitfield1:5; } IA32 representation :

7 6 5 4 3 2 1

PowerPC representation :

1 2 3 4 5 6 7

Endianness

Consider 0x12345678 Little endian : 0x78 0x56 0x34 0x12 Big endian : 0x12 0x34 0x56 0x78 PDP endian : 0x34 0x12 0x78 0x56

◮ External interfaces ◮ Use macros to convert between CPU and specific

endianess

Alignment

◮ Most RISC cpus require aligned accesses ◮ Unaligned accesses are trapped (mostly)

◮ Unaligned accesses are seldomly atomic with respect to

SMP/other bus masters

◮ Better

Intel style system

Intel style system

◮ Main components

◮ Main interfaces

Opteron style system

Opteron style system

◮ Main components

◮ Main interfaces

Trends in system design

◮ Observations

latencies

◮ Solutions

Out of order transactions

◮ examples

◮ use read/write barriers

possibly out of order : stw r20,0x20(r21) stw r22,0x24(r21) always in order : stw r20,0x20(r21) eieio stw r22,0x24(r21)

Non-coherent I/O

◮ Some systems do not support ”bus snooping” ◮ Invalidate cachelines

◮ non-cacheable memory

Addressing

◮ Virtual addresses ◮ Physical addresses ◮ Bus addresses ◮ Translation Physical to Bus addresses

◮ Always access hardware via special functions

Transaction atomicity

◮ Multiple CPUs ◮ other busmasters (eg. on PCI) ◮ reads and writes are atomic only if aligned ◮ atomic read/modify/write is CPU specific

◮ bridges may break locks

Userland hardware access

◮ Hardware access from userland is problematic ◮ Seperate command transport from driver logic

◮ Provide abstraction layer for accessing hardware