Investigations on possible HPD upgrade - ceramic carrier aspects A - - PowerPoint PPT Presentation

Investigations on possible HPD upgrade - ceramic carrier aspects A brief reminder and update

• T. Gys/CERN-PH

RICH electronics upgrade meeting CERN – 10 June 2010

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 2

Introduction

• What will be dealt with today:

– basic ceramic carrier aspects for “new HPD option 2” – related speed requirements aspects – related HPD manufacturing aspects

• What will not be dealt with today:

– overall HPD vacuum aspects – possible overall HPD design aspects – overall project aspects

• The following slides are the result of detailed on-going discussions with

Kyocera in liaison with Milano people (G. Pessina and C. Gotti)

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 3

PGA ZIF Socket

Pin-through electro-plating

LGA/BGA standard package or custom high-density PCB Printed circuit board

HPD part Vacuum-compatible External part No vacuum compatibility required Vacuum

HPD tube body HPD mechanical baseplate Detector chip ASIC chips

In Out

New HPD option 2: sketch - reminder

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 4

New HPD option 2 - reminder

• Anode design

– Pixel detector (only) encapsulated inside vacuum and directly bump-bonded to ceramic carrier (cf. 61- and 163-pixel HPDs) – Readout ASIC(s) external

• “Speed” requirements:

– Analogue data typ. <5000e- charge pulse – Maximize SNR and minimize cross-talk

• Notes/comments/concerns:

– Vacuum compatibility:

• Bake-out cycle (300°C) ⇒ high T bump-bonding (?)
• Outgassing properties after tube sealing

– No heat dissipation (transfer) issue from the vacuum to the external world

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 5

New HPD option 2 (2) – reminder + note

• Notes/comments/concerns (2):

– Speed limitations:

• Capacitive load to FE electronics
• Cross-talk
• PGA carrier:

– capacitive load increased by plating pattern (standard electro-plating cf 61-pixel carriers), can be minimized without plating pattern (pin-through electro-plating) – min. 1.27mm pin pitch (interstitial socket) – NOTE: previous carriers (61- and 163-pixels) were not optimized electrically: no guards, no ground planes, additional plating pattern, pin pattern not matching pixel pattern; maximum capacitive load 3.6pF for the 61-pixel carrier and between 3.5 and 6.2pF for the 163-pixel carrier

• ZIF socket/PCB/ASIC package and/or interface speed limitations – related ASIC FE

developments

– ZIF socket results in minimized mechanical stresses

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 6

New HPD option 2 (3) - reminder

• Notes/comments/concerns (3):

– Detector “packaging” in carrier:

• “Relaxed” bump-bonding process: typ. 400um bump size and 800um bump pitch

and compatibility with bake-out (300°C)

• Au-plating quality and compatibility with bake-out (300°C) ⇒ electro-plating

– Kovar ring interface and related mechanical, brazing (850°C) and welding aspects

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 7

Tentative pixel sensor: sketch - reminder

• Overall sensor 18mm active diameter
• Pixel:

– number: 490 (≤512) – size: 0.8mm flat-to-flat – capacitance «0.5pF

• Carrier output pins as close as possible to

pixels

• Carrier overall size 50mm sq. (similar to

current carrier)

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 8

Current status

• Preliminary carrier design from Kyocera, based on 490-pixel sensor

– made available on 31.10.2009 – additional info on capacitive load provided on 16.11.2009 – no feed-back to Kyocera until March 2010 – LHCb-RICH operations and HPD performance during LHC re-start took highest (and only) priority

• Basic features

– 490 pixel lines designed as transmission lines with guard and embedded within ground/power planes – 529 PGA (pixel lines + power and ground connections) with 15 layers – Design based on Z0=50 Ohms as a starting point – Characteristic impedance and capacitive load:

• Z0=50.4 Ohms
• C0=2.3pF/cm
• longest line 1.73cm – Cmax 3.98pF
• shortest line 0.19cm – Cmin 0.43pF
• lead-to-lead (signal-to-signal) capacitance Cm 0.02pF/cm

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 9

Current status (2)

• Preliminary S/N ratio estimate

– FE candidate: the key point (see presentation of C. Gotti dated 12.4.2010)

• charge-sensitive preamplifier in 90nm CMOS – expected back in August 2010
• tailored for diamond detector – 10ke- signal and C detector 1-5pF
• similar requirements for HPD with external readout
• expected performance – can “t” be even larger?

RICH upgrade electronics – T. Gys – 10.6.2010 Slide 10

Current status (3) and next plans

• On-going carrier design optimization

– Design relaxed on Z0>50 Ohms -> increased layer thickness – Suppress guards – yes or no? – Characteristic impedance and capacitive load:

• Z0=65.5 Ohms
• C0=1.6pF/cm
• longest line 1.73cm – Cmax 2.77pF
• shortest line 0.19cm – Cmin 0.30pF
• lead-to-lead (signal-to-signal) capacitance Cm 0.18pF/cm
• Prototyping

– Kyocera “cheap” test structures: not possible – Complete carrier prototype: expensive tooling charges – Use existing carriers (not optimized electrically) 61- or 163-pixel HPDs?

• Further FE design investigations
• Investigations on sensor packaging aspects (e.g. bump-bonding with

solder-jet technology)