.include "defines.h" .data hello: ta8 .string - PDF document

System call example הנבמ .include "defines.h" םיבשחמ .data hello: ta8 .string "hello world\n" .text .globl _start _start: movl $SYS_write,%eax // SYS_write = 4 Spring 200 6 movl $STDOUT,%ebx // fd = fileno(stdio) movl $hello,%ecx // buf = str Amar Lior movl $12,%edx // count = 0x6 int $0x80 movl $SYS_exit,%eax Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3 rd edition xorl %ebx,%ebx int $0x80 ret 1 4 Exceptions and Interrupts Program Flow Control � Exception: An unscheduled event that disrupts program execution and change its flow � Interrupts: An exception that comes from outside of the processor 2 5 Exception types: How Exception are Handled � Program � The address of the affected address is saved � e.g. overflow, division by zero, using undefined instruction in the EPC register � Invoking the operating system from user � The cause of the register is used to record program � systemcall � Timer the exception type. � Generated by internal processor timer � Than the process jump to the exception � Used in pre-emptive multi-tasking address which is the operating system entry � I/O � from I/O controller (keyboard, disk) point for exception handling � Hardware failure � In MIPS 0x8000 0180 � e.g. memory parity error � In SPIM 0x8000 0080 3 6 1

Interrupt Cycle Multiple Interrupts - Sequential � Added to instruction cycle � Processor checks for interrupt � Indicated by an interrupt signal � If no interrupt, fetch next instruction � If interrupt pending: � Suspend execution of current program � Save context � Set PC to start address of interrupt handler routine � Process interrupt � Restore context and continue interrupted program 7 10 Instruction Cycle (with Interrupts) - State Diagram Multiple Interrupts - Nested 8 11 Multiple Interrupts Example - PC Bus � Disable interrupts � Processor will ignore further interrupts whilst processing � 80x86 has one interrupt line one interrupt � 8086 based systems use one 8259A � Interrupts remain pending and are checked after first interrupt has been processed interrupt controller � Interrupts handled in sequence as they occur � 8259A has 8 interrupt lines � Define priorities � Called Programmable Interrupt Controller � Low priority interrupts can be interrupted by higher PIC in short. priority interrupts � When higher priority interrupt has been processed, processor returns to previous interrupt 9 12 2

Sequence of Events Exception Handling in MIPS (SPIM) � In MIPS processors, a part of the CPU called � 8259A accepts interrupts coprocessor 0 records the information that � 8259A determines priority software needs to handle exception � 8259A signals 8086 (raises INTR line) � Not all the coprocessor 0’s registers are implemented by SPIM � CPU Acknowledges � The mfc0 and mtc0 instructions are used to � 8259A puts correct vector on data bus access those registers � The EPC contain the address of the offending � CPU processes interrupt instruction (if the exception was internal) � And the address if the next instruction if the exception was external 13 16 PC Interrupt Layout Interrupt related registers Register Register Usage 8259A Name Number 8086 IRQ0 BadVAddr 8 Memory address at which offending memory reference System Timer occurred IRQ1 Keyboard Count 9 Timer IRQ2 Slave 8259A Compare 11 Value compared against timer that caused interrupt when IRQ3 INTR Serial port they match IRQ4 Serial port Status 12 Interrupt mask and enable bits IRQ5 IDE controller Cause 13 Exception type and pending interrupt bits IRQ6 Floppy controller IRQ7 Epc 14 Address of instruction that caused exception LPT1 14 17 The 8086 Interrupt table The Status Register � The interrupt mask contain a bit for each of the six hardware and two software � Fault – The return address point to the instruction that interrupt level caused the exception � Value of 1 means interrupt from that level can interrupt the processor � Trap – The return address points to the instruction after the � When an interrupt arrive it sets its “interrupt pending” bit in the cause register even if the mask is 0 one that caused the interrupt � When an interrupt is pending it will interrupt the processor when the mask is enabled. � The user mode is 0 when in kernel mode and 1 when in user mode (always 1 in spim) Number Description Type � The exception level is usually 0 but is set to 1 when exception occur, in this 0 Divide by zero Fault situation interrupts are disabled and the EPC is not updated if another exception occur. Enable exception handler from being disturbed by an Exception or 1 Debug exception Trap or Fault interrupt � If the interrupt enable bit is 1 interrupt are allowed 2 Trap Non-Maskable Interrupt (NMI) 3 Breakpoint Trap e n t d p o o i t u e r M p l l 4 Trap r Overflow e b r e e c v t a e n s x e n I e U E L 6 Trap Invalid opcode 15 8 4 1 0 14 Page Fault Fault 32-255 Available for software and hardware interrupts 15 18 Interrupt mask 3

Cause Register Exception handler example � The delayed branch is 1 if the last exception occurred in the delay slot of a branch � The interrupt pending bits become 1 when an interrupt is raised at a given hardware or software level � The exception code describe the cause of the exception through the codes in next slide 15 8 2 31 6 Branch Delay 19 Pending Interrupts Exception Code 22 Exception codes Number Name Cause of Exception 0 Int Interrupt (hardware) 4 AdEL Address error exception (load or fetch) 5 AdES Address error exception (store) 6 IBE Buss error in instruction fetch 7 DBE Buss error on data load or store 8 Sys Syscall exception 9 Bp Breakpoint exception 10 RI Reserved instruction exception 11 CpU Coprocessor unimplemented 12 Ov Arithmetic overflow exception 13 Tr Trap 15 FPE Floating point exception 20 Handling the Exception � Exception and interrupts cause the MIPS processor to jump to a piece of code at address 0x8000 0180 (kernel address space) � Called the exception handler � This code examine the exception’s code and jumps to an appropriate point in the operating system � The operating system respond by terminating the process or by performing some action 21 4