High-Frequency FOREX Trading: Identification of Triangular Arbitrage - - PowerPoint PPT Presentation

▶

May 30, 2023 111 likes •219 views

High-Frequency FOREX Trading: Identification of Triangular Arbitrage Opportunities Graham Gobieski, Kevin Kwan, Ziyi Zhu, Shang Liu Demos Demo 2 Demo 1 1 0 5 4 6 4 -13 0 1 -9 -9 1 1 4 1 1 2 3 2 2 3 -7 Destination 3 2 3

SLIDE 1

High-Frequency FOREX Trading:

Identification of Triangular Arbitrage Opportunities

Graham Gobieski, Kevin Kwan, Ziyi Zhu, Shang Liu

SLIDE 2

Demos

1 2 3 4 4 1 3 2 4 3

1 2 3 4 5 6 1 1 2

2 2 3 1 4

5 1 6 1

Demo 1 Demo 2

1 2 3 4

4 3 3

3 5 6 4 1 2

1 2

1 1

2 1

Destination Destination Source Source

SLIDE 3

Demo 3: Live Cycles

SLIDE 4

Motivation

High-Frequency Trading: taking

advantage of opportunities (inefficiencies, etc.) on very short timescales

Triangular Arbitrage: due to market

inefficiencies, exchanging a currency between three or more currencies and arriving back at the original currency might be profitable

Timescale: ~5-20ms, data streams
ver network

USD EUR AUD

0.978 1.06 1.02

1.02 x 1.06 x .978 > 1

SLIDE 5

Bellman-Ford

for each vertex x in V do if x is source then w(x) = 0 else w(x) = INFINITY p(x) = NULL end if end for for i = 1 to v - 1 do for each edge(i, j) in E do if w(i) + w(i, j) < w(j) then //Relaxation w(j) = w(i) + w(i, j) p(j) = i end if end for end for for each edge(i, j) in E do if w(j) > w(i) + w(i, j) then //Found Negative-Weight Cycle end if end for

Transformation

1. w1 * w2 * w3 * … * wn > 1
2. log(w1) + log(w2) + log(w3) + … + log(wn)< 0
3. -(log(w1) + log(w2) + log(w3) + … + log(wn))< 0

SLIDE 6

Hardware Design

Storage: SRAM Adjacency Matrix Vert List FOREX Container Frame Container

Update Adjacency Matrix

Bellman-Ford Cycle Detection Print Cycle Bellman-Ford Print-Cycle Cycle Detect Setup:

Src: 0 Other: Inf

Read:

Src and Dst

Relax:

w(src) + w(e) < w(dst)

Read:

Vertex

Test:

w(src) + w(e) < w(dst)

Read Cycle:

pred(dst)

Read:

Vertex

Test:

High bit is 1

Print:

frame_we <= 1 1 2 3 4 5 2a 2b 2c 3a 3b 3c 4a 4b 4c 5

Program Flow

VE Times V Times O(V) Times O(V) Times V Times 33 Nodes 33 Nodes 33 Nodes

SLIDE 7

Overview Print Cycle Bellman

SLIDE 8

Software Design, VGA

Hardware Python Front-End

1. Load Data 2. Preprocess Data 3. Write Data via custom Ioctl call

Kernel Module

1. Setup Memory- mapped I/O 2. Write Data to Bus

Amba Bus

Kernel Module 2

1. Setup Memory- mapped I/O 2. Write Key Data to Bus

C Front-End

1. Load Data 2. Preprocess Data 3. Write Data via custom Ioctl call 4. Write keyboard events

Amba Bus

Option 1 Option 2

SLIDE 9

RTL Synthesis

lab3:u0 clk_clk hps_io_hps_io_emac1_inst_RXD0 hps_io_hps_io_emac1_inst_RXD1 hps_io_hps_io_emac1_inst_RXD2 hps_io_hps_io_emac1_inst_RXD3 hps_io_hps_io_emac1_inst_RX_CLK hps_io_hps_io_emac1_inst_RX_CTL hps_io_hps_io_spim0_inst_MISO hps_io_hps_io_spim1_inst_MISO hps_io_hps_io_uart0_inst_RX hps_io_hps_io_usb1_inst_CLK hps_io_hps_io_usb1_inst_DIR hps_io_hps_io_usb1_inst_NXT memory_oct_rzqin reset_reset_n hps_io_hps_io_emac1_inst_MDC hps_io_hps_io_emac1_inst_MDIO hps_io_hps_io_emac1_inst_TXD0 hps_io_hps_io_emac1_inst_TXD1 hps_io_hps_io_emac1_inst_TXD2 hps_io_hps_io_emac1_inst_TXD3 hps_io_hps_io_emac1_inst_TX_CLK hps_io_hps_io_emac1_inst_TX_CTL hps_io_hps_io_i2c1_inst_SCL hps_io_hps_io_i2c1_inst_SDA hps_io_hps_io_qspi_inst_CLK hps_io_hps_io_qspi_inst_IO0 hps_io_hps_io_qspi_inst_IO1 hps_io_hps_io_qspi_inst_IO2 hps_io_hps_io_qspi_inst_IO3 hps_io_hps_io_qspi_inst_SS0 hps_io_hps_io_sdio_inst_CLK hps_io_hps_io_sdio_inst_CMD hps_io_hps_io_sdio_inst_D0 hps_io_hps_io_sdio_inst_D1 hps_io_hps_io_sdio_inst_D2 hps_io_hps_io_sdio_inst_D3 hps_io_hps_io_spim0_inst_CLK hps_io_hps_io_spim0_inst_MOSI hps_io_hps_io_spim0_inst_SS0 hps_io_hps_io_spim1_inst_CLK hps_io_hps_io_spim1_inst_MOSI hps_io_hps_io_spim1_inst_SS0 hps_io_hps_io_uart0_inst_TX hps_io_hps_io_usb1_inst_D0 hps_io_hps_io_usb1_inst_D1 hps_io_hps_io_usb1_inst_D2 hps_io_hps_io_usb1_inst_D3 hps_io_hps_io_usb1_inst_D4 hps_io_hps_io_usb1_inst_D5 hps_io_hps_io_usb1_inst_D6 hps_io_hps_io_usb1_inst_D7 hps_io_hps_io_usb1_inst_STP memory_mem_cas_n memory_mem_ck memory_mem_ck_n memory_mem_cke memory_mem_cs_n memory_mem_odt memory_mem_ras_n memory_mem_reset_n memory_mem_we_n vga_BLANK_n vga_CLK vga_HS vga_SYNC_n vga_VS memory_mem_a[14..0] memory_mem_ba[2..0] memory_mem_dm[3..0] vga_R[7..0] vga_G[7..0] vga_B[7..0] memory_mem_dq[31..0] memory_mem_dqs[3..0] memory_mem_dqs_n[3..0] FOREX:frame_0 chipselect clk reset write writedata[31..0] address[2..0] VGA_BLANK_n VGA_CLK VGA_HS VGA_SYNC_n VGA_VS VGA_R[7..0] VGA_G[7..0] VGA_B[7..0] Container:container clk container_reset src[6..0] 7'h0 u_src[6..0] u_dst[6..0] u_e[31..0] frame_we frame_char[5..0] frame_x[5..0] frame_y[5..0] AUD_DACDAT 1'h0 AUD_DACLRCK AUD_I2C_SCLK 1'h0 AUD_I2C_SDAT AUD_MUTE 1'h0 AUD_XCK 1'h0 + Add0 A[19..0] B[19..0] 20'h80000 OUT[19..0] = Equal0 A[19..0] B[19..0] 20'hfffff OUT FAN_CTRL 1'h0 HSMC_CLKIN_n[2..1] HSMC_CLKIN_p[2..1] HSMC_CLKOUT_n[2..1] 2'h0 HSMC_CLKOUT_p[2..1] 2'h0 HSMC_CLK_IN0 HSMC_CLK_OUT0 1'h0 HSMC_D[3..0] HSMC_RX_n[16..0] HSMC_RX_p[16..0] HSMC_SCL 1'h0 HSMC_SDA HSMC_TX_n[16..0] HSMC_TX_p[16..0] IRDA_RXD KEY[3..0] LED[3..0] OSC_50_B3B OSC_50_B4A OSC_50_B5B OSC_50_B8A PCIE_PERST_n PCIE_WAKE_n RESET_n SI5338_SCL SI5338_SDA SW[3..0] TEMP_CS_n 1'h0 TEMP_DIN 1'h0 TEMP_DOUT TEMP_SCLK 1'h0 USB_B2_CLK USB_B2_DATA[7..0] USB_EMPTY 1'h0 USB_FULL 1'h0 USB_OE_n USB_RD_n USB_RESET_n USB_SCL USB_SDA USB_WR_n VGA_BLANK_n VGA_B[7..0] VGA_CLK VGA_G[7..0] VGA_HS VGA_R[7..0] VGA_SYNC_n VGA_VS hps_fpga_reset_n 1 1'h1 hps_fpga_reset_n D CLK Q hps_io_hps_io_emac1_inst_MDC hps_io_hps_io_emac1_inst_MDIO hps_io_hps_io_emac1_inst_RXD0 hps_io_hps_io_emac1_inst_RXD1 hps_io_hps_io_emac1_inst_RXD2 hps_io_hps_io_emac1_inst_RXD3 hps_io_hps_io_emac1_inst_RX_CLK hps_io_hps_io_emac1_inst_RX_CTL hps_io_hps_io_emac1_inst_TXD0 hps_io_hps_io_emac1_inst_TXD1 hps_io_hps_io_emac1_inst_TXD2 hps_io_hps_io_emac1_inst_TXD3 hps_io_hps_io_emac1_inst_TX_CLK hps_io_hps_io_emac1_inst_TX_CTL hps_io_hps_io_gpio_inst_GPIO00 hps_io_hps_io_i2c1_inst_SCL hps_io_hps_io_i2c1_inst_SDA hps_io_hps_io_qspi_inst_CLK hps_io_hps_io_qspi_inst_IO0 hps_io_hps_io_qspi_inst_IO1 hps_io_hps_io_qspi_inst_IO2 hps_io_hps_io_qspi_inst_IO3 hps_io_hps_io_qspi_inst_SS0 hps_io_hps_io_sdio_inst_CLK hps_io_hps_io_sdio_inst_CMD hps_io_hps_io_sdio_inst_D0 hps_io_hps_io_sdio_inst_D1 hps_io_hps_io_sdio_inst_D2 hps_io_hps_io_sdio_inst_D3 hps_io_hps_io_spim0_inst_CLK hps_io_hps_io_spim0_inst_MISO hps_io_hps_io_spim0_inst_MOSI hps_io_hps_io_spim0_inst_SS0 hps_io_hps_io_spim1_inst_CLK hps_io_hps_io_spim1_inst_MISO hps_io_hps_io_spim1_inst_MOSI hps_io_hps_io_spim1_inst_SS0 hps_io_hps_io_uart0_inst_RX hps_io_hps_io_uart0_inst_TX hps_io_hps_io_usb1_inst_CLK hps_io_hps_io_usb1_inst_DIR hps_io_hps_io_usb1_inst_D0 hps_io_hps_io_usb1_inst_D1 hps_io_hps_io_usb1_inst_D2 hps_io_hps_io_usb1_inst_D3 hps_io_hps_io_usb1_inst_D4 hps_io_hps_io_usb1_inst_D5 hps_io_hps_io_usb1_inst_D6 hps_io_hps_io_usb1_inst_D7 hps_io_hps_io_usb1_inst_NXT hps_io_hps_io_usb1_inst_STP hps_reset_counter[19..0] D CLK Q memory_oct_rzqin memory_mem_we_n memory_mem_reset_n AdjMat:adjmat clk we data[31..0] row_addr[6..0] col_addr[6..0] q[31..0] Bellman:bellman bellman_reset clk src[6..0] vertmat_q_a[39..0] vertmat_q_b[39..0] adjmat_q[31..0] bellman_done vertmat_we_a vertmat_we_b vertmat_data_a[39..0] vertmat_data_b[39..0] vertmat_addr_a[6..0] vertmat_addr_b[6..0] adjmat_row_addr[6..0] adjmat_col_addr[6..0] CycleDetect:cycle_detect clk cycle_reset vertmat_q_a[39..0] vertmat_q_b[39..0] adjmat_q[31..0] cycle_done vertmat_we_b vertmat_addr_a[6..0] vertmat_addr_b[6..0] vertmat_data_b[39..0] adjmat_row_addr[6..0] adjmat_col_addr[6..0] PrintCycle:print_cycle clk print_reset vertmat_q_b[39..0] frame_we print_done vertmat_we_b vertmat_data_b[39..0] vertmat_addr_b[6..0] frame_char[5..0] frame_x[5..0] frame_y[5..0] Selector7 SEL[2..0] DATA[2..0] OUT Selector11 SEL[2..0] DATA[2..0] OUT Selector12 SEL[2..0] DATA[2..0] OUT Selector13 SEL[4..0] DATA[4..0] OUT Selector14 SEL[4..0] DATA[4..0] OUT Selector15 SEL[4..0] DATA[4..0] OUT Selector16 SEL[4..0] DATA[4..0] OUT Selector17 SEL[4..0] DATA[4..0] OUT Selector18 SEL[4..0] DATA[4..0] OUT Selector19 SEL[4..0] DATA[4..0] OUT Selector20 SEL[4..0] DATA[4..0] OUT Selector21 SEL[4..0] DATA[4..0] OUT Selector22 SEL[4..0] DATA[4..0] OUT Selector23 SEL[4..0] DATA[4..0] OUT Selector24 SEL[4..0] DATA[4..0] OUT Selector25 SEL[4..0] DATA[4..0] OUT Selector26 SEL[4..0] DATA[4..0] OUT Selector27 SEL[2..0] DATA[2..0] OUT Selector28 SEL[2..0] DATA[2..0] OUT Selector29 SEL[2..0] DATA[2..0] OUT Selector30 SEL[2..0] DATA[2..0] OUT Selector31 SEL[2..0] DATA[2..0] OUT Selector32 SEL[2..0] DATA[2..0] OUT Selector33 SEL[2..0] DATA[2..0] OUT Selector34 SEL[3..0] DATA[3..0] OUT Selector35 SEL[3..0] DATA[3..0] OUT Selector36 SEL[3..0] DATA[3..0] OUT Selector37 SEL[3..0] DATA[3..0] OUT Selector38 SEL[3..0] DATA[3..0] OUT Selector39 SEL[3..0] DATA[3..0] OUT Selector40 SEL[3..0] DATA[3..0] OUT Selector41 SEL[3..0] DATA[3..0] OUT Selector42 SEL[3..0] DATA[3..0] OUT Selector43 SEL[3..0] DATA[3..0] OUT Selector44 SEL[3..0] DATA[3..0] OUT Selector45 SEL[3..0] DATA[3..0] OUT Selector46 SEL[3..0] DATA[3..0] OUT Selector47 SEL[3..0] DATA[3..0] OUT Selector48 SEL[3..0] DATA[3..0] OUT Selector49 SEL[3..0] DATA[3..0] OUT Selector50 SEL[3..0] DATA[3..0] OUT Selector51 SEL[3..0] DATA[3..0] OUT Selector52 SEL[3..0] DATA[3..0] OUT Selector53 SEL[3..0] DATA[3..0] OUT Selector54 SEL[3..0] DATA[3..0] OUT Selector55 SEL[3..0] DATA[3..0] OUT Selector56 SEL[3..0] DATA[3..0] OUT Selector57 SEL[3..0] DATA[3..0] OUT Selector58 SEL[3..0] DATA[3..0] OUT Selector59 SEL[3..0] DATA[3..0] OUT Selector60 SEL[3..0] DATA[3..0] OUT Selector61 SEL[3..0] DATA[3..0] OUT Selector62 SEL[3..0] DATA[3..0] OUT Selector63 SEL[3..0] DATA[3..0] OUT Selector64 SEL[3..0] DATA[3..0] OUT Selector65 SEL[3..0] DATA[3..0] OUT Selector66 SEL[3..0] DATA[3..0] OUT Selector67 SEL[3..0] DATA[3..0] OUT Selector68 SEL[3..0] DATA[3..0] OUT Selector69 SEL[3..0] DATA[3..0] OUT Selector70 SEL[3..0] DATA[3..0] OUT Selector71 SEL[3..0] DATA[3..0] OUT Selector72 SEL[3..0] DATA[3..0] OUT Selector73 SEL[3..0] DATA[3..0] OUT Selector74 SEL[3..0] DATA[3..0] OUT Selector75 SEL[3..0] DATA[3..0] OUT Selector76 SEL[3..0] DATA[3..0] OUT Selector77 SEL[3..0] DATA[3..0] OUT Selector78 SEL[3..0] DATA[3..0] OUT Selector79 SEL[3..0] DATA[3..0] OUT Selector80 SEL[3..0] DATA[3..0] OUT Selector81 SEL[3..0] DATA[3..0] OUT VertMat:vertmat clk we_a we_b data_a[39..0] data_b[39..0] addr_a[6..0] addr_b[6..0] q_a[39..0] q_b[39..0] WideNor0 WideOr1 WideOr3 WideOr4 WideOr5 WideOr6 WideOr7 WideOr8 WideOr9 WideOr10 WideOr11 WideOr12 WideOr13 WideOr14 WideOr15 WideOr16 WideOr17 WideOr18 WideOr19 WideOr20 WideOr21 WideOr22 WideOr23 WideOr24 WideOr25 WideOr26 WideOr27 WideOr28 WideOr29 WideOr30 WideOr31 WideOr32 WideOr33 WideOr34 WideOr35 WideOr36 WideOr37 WideOr38 WideOr39 WideOr40 WideOr41 WideOr42 WideOr43 WideOr44 WideOr45 WideOr46 WideOr47 WideOr48 WideOr49 WideOr50 WideOr51 WideOr52 WideOr53 WideOr54 WideOr55 WideOr56 WideOr57 WideOr58 WideOr59 adjmat_col_addr~0 adjmat_col_addr~1 adjmat_col_addr~2 adjmat_col_addr~3 adjmat_col_addr~4 adjmat_col_addr~5 adjmat_col_addr~6 adjmat_data[31..0] 32'h0 1 adjmat_row_addr~0 adjmat_row_addr~1 adjmat_row_addr~2 adjmat_row_addr~3 adjmat_row_addr~4 adjmat_row_addr~5 adjmat_row_addr~6 adjmat_we bellman_reset D CLK ENA Q container_done~reg0 D CLK Q container_done~0 1 1'h1 container_done~1 1 1'h0 cycle_reset 1 1'h1 cycle_reset D CLK ENA Q next_state Bellman:bellman clk container_reset CycleDetect:cycle_detect state.DONE state.IDLE state.RUN_BELLMAN state.RUN_CYCLE_DETECT state.RUN_PRINT_CYCLE state.UPDATE_FOR state.UPDATE_REV RUN_BELLMAN RUN_CYCLE_DETECT RUN_PRINT_CYCLE print_reset 1 1'h1 print_reset D CLK ENA Q state Bellman:bellman clk container_reset CycleDetect:cycle_detect next_state next_state next_state PrintCycle:print_cycle DONE IDLE RUN_BELLMAN RUN_CYCLE_DETECT RUN_PRINT_CYCLE UPDATE_FOR UPDATE_REV = Equal0 A[2..0] B[2..0] 3'h0 OUT = Equal1 A[2..0] B[2..0] 3'h4 OUT Frame:buffer clk reset we x[5..0] y[5..0] char[5..0] VGA_BLANK_n VGA_CLK VGA_HS VGA_SYNC_n VGA_VS VGA_R[7..0] VGA_G[7..0] VGA_B[7..0] Selector0 SEL[2..0] DATA[2..0] OUT always0 container_reset D CLK Q next_state clk state.RESET CONTAINER state always0 clk next_state reset address[2..0] CONTAINER IDLE RESET u_dst[6..0] D CLK ENA Q u_dst~0 1 u_dst~1 1 u_dst~2 1 u_dst~3 1 u_dst~4 1 u_dst~5 1 u_dst~6 1 u_dst~7 1 u_dst~8 1 u_dst~9 1 u_dst~10 1 u_dst~11 1 u_dst~12 1 u_dst~13 1 u_e[31..0] D CLK ENA Q u_e~0 1 u_e~1 1 u_e~2 1 u_e~3 1 u_e~4 1 u_e~5 1 u_e~6 1 u_e~7 1 u_e~8 1 u_e~9 1 u_e~10 1 u_e~11 1 u_e~12 1 u_e~13 1 u_e~14 1 u_e~15 1 u_e~16 1 u_e~17 1 u_e~18 1 u_e~19 1 u_e~20 1 u_e~21 1 u_e~22 1 u_e~23 1 u_e~24 1 u_e~25 1 u_e~26 1 u_e~27 1 u_e~28 1 u_e~29 1 u_e~30 1 u_e~31 1 u_e~32 1 u_e~33 1 u_e~34 1 u_e~35 1 u_e~36 1 u_e~37 1 u_e~38 1 u_e~39 1 u_e~40 1 u_e~41 1 u_e~42 1 u_e~43 1 u_e~44 1 u_e~45 1 u_e~46 1 u_e~47 1 u_e~48 1 u_e~49 1 u_e~50 1 u_e~51 1 u_e~52 1 u_e~53 1 u_e~54 1 u_e~55 1 u_e~56 1 u_e~57 1 u_e~58 1 u_e~59 1 u_e~60 1 u_e~61 1 u_e~62 1 u_e~63 1 u_src[6..0] D CLK ENA Q u_src~0 1 u_src~1 1 u_src~2 1 u_src~3 1 u_src~4 1 u_src~5 1 u_src~6 1 u_src~7 1 u_src~8 1 u_src~9 1 u_src~10 1 u_src~11 1 u_src~12 1 u_src~13 1 altera_reset_controller:rst_controller_001 clk reset_in0 reset_in1 1'h0 reset_in10 1'h0 reset_in11 1'h0 reset_in12 1'h0 reset_in13 1'h0 reset_in14 1'h0 reset_in15 1'h0 reset_in2 1'h0 reset_in3 1'h0 reset_in4 1'h0 reset_in5 1'h0 reset_in6 1'h0 reset_in7 1'h0 reset_in8 1'h0 reset_in9 1'h0 reset_req_in0 1'h0 reset_req_in1 1'h0 reset_req_in10 1'h0 reset_req_in11 1'h0 reset_req_in12 1'h0 reset_req_in13 1'h0 reset_req_in14 1'h0 reset_req_in15 1'h0 reset_req_in2 1'h0 reset_req_in3 1'h0 reset_req_in4 1'h0 reset_req_in5 1'h0 reset_req_in6 1'h0 reset_req_in7 1'h0 reset_req_in8 1'h0 reset_req_in9 1'h0 reset_out altera_reset_controller:rst_controller clk reset_in0 reset_in1 1'h0 reset_in10 1'h0 reset_in11 1'h0 reset_in12 1'h0 reset_in13 1'h0 reset_in14 1'h0 reset_in15 1'h0 reset_in2 1'h0 reset_in3 1'h0 reset_in4 1'h0 reset_in5 1'h0 reset_in6 1'h0 reset_in7 1'h0 reset_in8 1'h0 reset_in9 1'h0 reset_req_in0 1'h0 reset_req_in1 1'h0 reset_req_in10 1'h0 reset_req_in11 1'h0 reset_req_in12 1'h0 reset_req_in13 1'h0 reset_req_in14 1'h0 reset_req_in15 1'h0 reset_req_in2 1'h0 reset_req_in3 1'h0 reset_req_in4 1'h0 reset_req_in5 1'h0 reset_req_in6 1'h0 reset_req_in7 1'h0 reset_req_in8 1'h0 reset_req_in9 1'h0 reset_out lab3_hps_0:hps_0 f2h_axi_clk h2f_axi_clk h2f_lw_ARREADY h2f_lw_AWREADY h2f_lw_BVALID h2f_lw_RLAST h2f_lw_RVALID h2f_lw_WREADY h2f_lw_axi_clk hps_io_emac1_inst_RXD0 hps_io_emac1_inst_RXD1 hps_io_emac1_inst_RXD2 hps_io_emac1_inst_RXD3 hps_io_emac1_inst_RX_CLK hps_io_emac1_inst_RX_CTL hps_io_spim0_inst_MISO hps_io_spim1_inst_MISO hps_io_uart0_inst_RX hps_io_usb1_inst_CLK hps_io_usb1_inst_DIR hps_io_usb1_inst_NXT

ct_rzqin

f2h_AWID[7..0] f2h_AWADDR[31..0] f2h_AWLEN[3..0] f2h_AWSIZE[2..0] f2h_AWBURST[1..0] f2h_AWLOCK[1..0] f2h_AWCACHE[3..0] f2h_AWPROT[2..0] f2h_AWUSER[4..0] f2h_WID[7..0] f2h_WDATA[63..0] f2h_WSTRB[7..0] f2h_ARID[7..0] f2h_ARADDR[31..0] f2h_ARLEN[3..0] f2h_ARSIZE[2..0] f2h_ARBURST[1..0] f2h_ARLOCK[1..0] f2h_ARCACHE[3..0] f2h_ARPROT[2..0] f2h_ARUSER[4..0] h2f_lw_BID[11..0] h2f_lw_BRESP[1..0] h2f_lw_RID[11..0] h2f_lw_RDATA[31..0] h2f_lw_RRESP[1..0] h2f_BID[11..0] h2f_BRESP[1..0] h2f_RID[11..0] h2f_RDATA[63..0] h2f_RRESP[1..0] f2h_irq_p0[31..0] f2h_irq_p1[31..0] h2f_lw_ARVALID h2f_lw_AWVALID h2f_lw_BREADY h2f_lw_RREADY h2f_lw_WLAST h2f_lw_WVALID h2f_rst_n hps_io_emac1_inst_MDC hps_io_emac1_inst_MDIO hps_io_emac1_inst_TXD0 hps_io_emac1_inst_TXD1 hps_io_emac1_inst_TXD2 hps_io_emac1_inst_TXD3 hps_io_emac1_inst_TX_CLK hps_io_emac1_inst_TX_CTL hps_io_i2c1_inst_SCL hps_io_i2c1_inst_SDA hps_io_qspi_inst_CLK hps_io_qspi_inst_IO0 hps_io_qspi_inst_IO1 hps_io_qspi_inst_IO2 hps_io_qspi_inst_IO3 hps_io_qspi_inst_SS0 hps_io_sdio_inst_CLK hps_io_sdio_inst_CMD hps_io_sdio_inst_D0 hps_io_sdio_inst_D1 hps_io_sdio_inst_D2 hps_io_sdio_inst_D3 hps_io_spim0_inst_CLK hps_io_spim0_inst_MOSI hps_io_spim0_inst_SS0 hps_io_spim1_inst_CLK hps_io_spim1_inst_MOSI hps_io_spim1_inst_SS0 hps_io_uart0_inst_TX hps_io_usb1_inst_D0 hps_io_usb1_inst_D1 hps_io_usb1_inst_D2 hps_io_usb1_inst_D3 hps_io_usb1_inst_D4 hps_io_usb1_inst_D5 hps_io_usb1_inst_D6 hps_io_usb1_inst_D7 hps_io_usb1_inst_STP mem_cas_n mem_ck mem_ck_n mem_cke mem_cs_n mem_odt mem_ras_n mem_reset_n mem_we_n f2h_BID[7..0] f2h_BRESP[1..0] f2h_RID[7..0] f2h_RDATA[63..0] f2h_RRESP[1..0] h2f_lw_AWID[11..0] h2f_lw_AWADDR[20..0] h2f_lw_AWLEN[3..0] h2f_lw_AWSIZE[2..0] h2f_lw_AWBURST[1..0] h2f_lw_AWLOCK[1..0] h2f_lw_AWCACHE[3..0] h2f_lw_AWPROT[2..0] h2f_lw_WID[11..0] h2f_lw_WDATA[31..0] h2f_lw_WSTRB[3..0] h2f_lw_ARID[11..0] h2f_lw_ARADDR[20..0] h2f_lw_ARLEN[3..0] h2f_lw_ARSIZE[2..0] h2f_lw_ARBURST[1..0] h2f_lw_ARLOCK[1..0] h2f_lw_ARCACHE[3..0] h2f_lw_ARPROT[2..0] h2f_AWID[11..0] h2f_AWADDR[29..0] h2f_AWLEN[3..0] h2f_AWSIZE[2..0] h2f_AWBURST[1..0] h2f_AWLOCK[1..0] h2f_AWCACHE[3..0] h2f_AWPROT[2..0] h2f_WID[11..0] h2f_WDATA[63..0] h2f_WSTRB[7..0] h2f_ARID[11..0] h2f_ARADDR[29..0] h2f_ARLEN[3..0] h2f_ARSIZE[2..0] h2f_ARBURST[1..0] h2f_ARLOCK[1..0] h2f_ARCACHE[3..0] h2f_ARPROT[2..0] mem_a[14..0] mem_ba[2..0] mem_dm[3..0] mem_dq[31..0] mem_dqs[3..0] mem_dqs_n[3..0] lab3_irq_mapper:irq_mapper_001 sender_irq[31..0] lab3_irq_mapper:irq_mapper sender_irq[31..0] lab3_master_0:master_0 clk_clk clk_reset_reset master_readdatavalid master_waitrequest master_readdata[31..0] master_read master_write master_address[31..0] master_writedata[31..0] master_byteenable[3..0] lab3_mm_interconnect_0:mm_interconnect_0 Frame_0_reset_sink_reset_bridge_in_reset_reset clk_0_clk_clk hps_0_h2f_lw_axi_master_agent_clk_reset_reset_bridge_in_reset_reset hps_0_h2f_lw_axi_master_arvalid hps_0_h2f_lw_axi_master_awvalid hps_0_h2f_lw_axi_master_bready hps_0_h2f_lw_axi_master_rready hps_0_h2f_lw_axi_master_wlast hps_0_h2f_lw_axi_master_wvalid master_0_clk_reset_reset_bridge_in_reset_reset master_0_master_read master_0_master_write hps_0_h2f_lw_axi_master_awid[11..0] hps_0_h2f_lw_axi_master_awaddr[20..0] hps_0_h2f_lw_axi_master_awlen[3..0] hps_0_h2f_lw_axi_master_awsize[2..0] hps_0_h2f_lw_axi_master_awburst[1..0] hps_0_h2f_lw_axi_master_awlock[1..0] hps_0_h2f_lw_axi_master_awcache[3..0] hps_0_h2f_lw_axi_master_awprot[2..0] hps_0_h2f_lw_axi_master_wid[11..0] hps_0_h2f_lw_axi_master_wdata[31..0] hps_0_h2f_lw_axi_master_wstrb[3..0] hps_0_h2f_lw_axi_master_arid[11..0] hps_0_h2f_lw_axi_master_araddr[20..0] hps_0_h2f_lw_axi_master_arlen[3..0] hps_0_h2f_lw_axi_master_arsize[2..0] hps_0_h2f_lw_axi_master_arburst[1..0] hps_0_h2f_lw_axi_master_arlock[1..0] hps_0_h2f_lw_axi_master_arcache[3..0] hps_0_h2f_lw_axi_master_arprot[2..0] master_0_master_address[31..0] master_0_master_byteenable[3..0] master_0_master_writedata[31..0] Frame_0_avalon_slave_0_chipselect Frame_0_avalon_slave_0_write hps_0_h2f_lw_axi_master_arready hps_0_h2f_lw_axi_master_awready hps_0_h2f_lw_axi_master_bvalid hps_0_h2f_lw_axi_master_rlast hps_0_h2f_lw_axi_master_rvalid hps_0_h2f_lw_axi_master_wready master_0_master_readdatavalid master_0_master_waitrequest hps_0_h2f_lw_axi_master_bid[11..0] hps_0_h2f_lw_axi_master_bresp[1..0] hps_0_h2f_lw_axi_master_rid[11..0] hps_0_h2f_lw_axi_master_rdata[31..0] hps_0_h2f_lw_axi_master_rresp[1..0] master_0_master_readdata[31..0] Frame_0_avalon_slave_0_address[2..0] Frame_0_avalon_slave_0_writedata[31..0] memory_mem_a[14..0] memory_mem_ba[2..0] memory_mem_cas_n memory_mem_ck_n memory_mem_cke memory_mem_ck memory_mem_cs_n memory_mem_dm[3..0] memory_mem_dq[31..0] memory_mem_dqs[3..0] memory_mem_dqs_n[3..0] memory_mem_odt memory_mem_ras_n AUD_BCLK AUD_ADCLRCK AUD_ADCDAT 13 12 11 10 9 8 7 6 5 3 2 1 4 31 30 29 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 6 5 4 3 2 1 6 5 4 3 2 1 31 30 29 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 28 27 26 25 24 23 22 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 29 30 31 6 5 3 2 1 4 6 5 3 2 1 4

FOREX Container

Other Modules

SLIDE 10

Challenges

Obviously Timing…
Memory Accesses
Nested Non-blocking Assignments
Combinational Logic and Sequential Logic Working

Together

Compile Time