HDI Hig h De n sity In te rcon n e ct Ole Kristia n Ha m re - - PowerPoint PPT Presentation

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HDI Hig h De n sity In te rcon n e ct Ole Kristia n Ha m re - - PowerPoint PPT Presentation

Feb 07, 2023 280 likes •690 views

HDI Hig h De n sity In te rcon n e ct Ole Kristia n Ha m re Srlie UiO, 0 2/0 4 -20 19 w w w .rd -d a ta re sp on s.n o 1 1. In trod u ction to HDI 2. Usin g HDI in circu it d e sig n AGENDA 3. Use of HDI in a p roje ct 4 . Le

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HDI

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Hig h De n sity In te rcon n e ct

Ole Kristia n Ha m re Sørlie UiO, 0 2/0 4 -20 19

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AGENDA

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1. In trod u ction to HDI

  • 2. Usin g HDI in circu it d e sig n
  • 3. Use of HDI in a p roje ct

4 . Le sson s le a rn e d

  • 5. Con clu sion
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What is HDI?

  • High Density Interconnect
  • Advanced PCB technology
  • Simply put:
  • Smaller vias, both blind and buried
  • Smaller traces
  • Can reduce PCB area and layers needed
  • More reliable
  • Becoming more cost effective

From the HDI Handbook

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History of HDI

  • HP FINSTRATE (1984) 32-bit computer
  • 1990s
  • Used in early Sony camcorders (1996)
  • Rapid growth from 2000
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Related IPC standards

  • IPC/JPCA-2315: Design Guide for High-density Interconnect Structures and Microvias
  • IPC-2226: Sectional Design Standard for High-density Interconnect (HDI) Printed Boards
  • IPC/JPCA-4104: Qualification and Performance Specification for Dielectric Materials for

High-density Interconnect Structures (HDI)

  • IPC-6016: Qualification and Performance Specification for High-density Interconnect

(HDI) Structures

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IPC-2226 Definition of HDI

  • PCB with finer lines and spaces ≤ 100 um
  • Vias are ≤ 150 um and capture pads are < 400 um
  • Higher connection pad density than conventional PCB (>20 pads/cm^2)
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IPC-2226 Definition of Microvia

  • Has a capture pad diameter ≤ 350 um
  • Has a plated hole with a diameter ≤ 150 um formed either by laser or

mechanical drilling

  • Hole with an aspect ratio of 1:1 (normal PTH typically 10:1)
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Via types

  • Plated through hole via (PTH): Outer layer to outer layer
  • Blind via: Outer layer to inner layer
  • Buried via: Inner layer to inner layer
  • Microvias
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Via aspect ratio (AR)

  • Defined as the relationship between the diameter of the hole and its length.
  • Usually in the range of 6:1 to 10:1 for PTH
  • 10:1 is the minimum for PTH (lower reliability)
  • 6:1 recommended for highest reliability
  • Thicker board = larger vias
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Microvias

  • AR of 1:1 / 1:0.8
  • Staggered
  • Copper filled (via-in-pad)
  • Stacked
  • Skip
  • Buried

From Interrupt Inside: High Density Interconnect - Haldor Husby

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HDI PCB Fabrication process

Core -> Buried vias filled-> Hot pressed together

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PCB fabrication costs

  • Blind Vias (+20% to +40% fabrication cost)
  • Buried Vias (+25% to +60% fabrication cost)
  • Micro Vias (+30% fabrication cost)
  • Back-drilled Vias (+10% fabrication cost)
  • Via-In-Pad (+30% fabrication cost)
  • Extra Layers (+20% fabrication cost (per every two layers)

Cost estimates from Xilinx

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IPC-2226 HDI Type I and II

  • Type I: One HDI layer on top and/or bottom with

through-vias from surface to surface.

  • Type II: One HDI layer on top and/or bottom with buried

vias in the core and may have through-vias connecting the outer layers from surface to surface.

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IPC-2226 HDI Type III

  • Most used type
  • Two or more HDI layers added to through-vias in the

core or from surface to surface

  • Buried vias
  • Stacked microvias
  • Used on the project described in this presentation
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IPC-2226 HDI Type IV, V and VI

  • Less used
  • Type IV: Passive core substrate with no electrical connecting functions.
  • Type V: Coreless constructions using layer pairs.
  • Type VI: Alternate constructions of coreless construction using layer pairs.

Type IV Type V Type VI

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BGA breakout aspects

  • Route density
  • Cost
  • Signal Integrity
  • Power Integrity
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Breakout patterns

  • Adjacent (dog-bone)
  • Partial via-in-pad
  • Via-in-pad (centered)

Dog-bone Partial via-in-pad Via-in-pad

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PTH vs Microvia breakout

  • Smaller capture pad
  • Routing of multiple traces
  • 10:1 vs 1:0.8 AR

From Interrupt Inside: High Density Interconnect - Haldor Husby From IPC-2226

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How many signal layers are needed?

BGA Pitch 0.8mm - 20 x 20 rows Standard PTH, dogbone technique From the Wurth HDI Webinar “Dogbone” fan out

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How many signal layers are needed?

BGA Pitch 0.8mm - 20 x 20 rows Microvia, via in pad allows two tracks between the vias From the Wurth HDI Webinar

Note: Example above requires stacked microvias, which adds some additional cost and affects overall reliability

Via in pad

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Not just for BGA...

From the Wurth HDI Webinar QFN with Microvia (via in pad) QFN with PTH

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High speed / signal integrity

  • HDI instead of expensive high frequency material
  • Via in pads, shorter trace lengths
  • Remove via stubs
  • Avoid backdrilling of vias

From the Wurth HDI Webinar

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Reliability

  • Vias especially important
  • Ranked most robust to least:

1. Micro via 2. Staggered microvia 3. Through hole via 4. Stacked microvia 5. Blind via 6. Buried via

Thermal expansion of PCB material (ie during reflow) -> From Haldor Husby Reliability presentation

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Via-in-pad filling

  • Gassing during reflow caused by an unfilled via-in-pad, causing excessive package movement
  • Can be prevented by precise control of flux/solder paste and reflow temperature profile
  • Or by copper/epoxy filling (extra cost)

From the Wurth HDI Webinar

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Acoustic sensor project

  • Acoustic data measurement
  • Record and store acoustic data through multiple sensors
  • Continuous operation for several weeks
  • Several terabytes of data
  • Schematic by Data Respons, PCB layout by Asian company
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Functional block diagram

  • Acoustic Data Collection module
  • Xilinx Ultrascale SoC
  • 32 transducers
  • LPDDR4
  • eMMC, QSPI
  • Ethernet, PCIe
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Proposed floorplan

  • 110mm x 250 mm
  • ~5000 components
  • Very high density board
  • Big challenge for Asian company
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PCB Specifications

  • 14 layer
  • FR-4
  • L1-L2 & L2-L3 and symmetric on bottom layers.
  • Type III HDI
  • No stacked microvia or microvia on buried via

(reliability)

  • Outer vias filled and capped (allows via-in-pad)
  • Buried microvias not filled or capped
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SoC BGA Breakout

  • 0.8mm pitch
  • 28x28, 784 pin BGA
  • Ground and VCC pins sprinkled around

Xilinx SoC pinout

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PCB layout process

  • Communication primarily through Confluence
  • No direct contact with PCB manufacturer
  • NCAB HDI PCB design rules
  • Language barrier
  • Layout comments in Confluence
  • BGA breakout mix of via-in-pad and buried vias
  • Overworked layout designers

Top Layer Layer 3 Layer 4

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Asian PCB manufacturing issues

  • Chinese HDI manufacturers overloaded (bitcoin craze)
  • Small prototype runs was a low priority
  • 5 weeks lead time
  • Failed to meet the required10% accuracy of impedance
  • All boards scrapped without question...
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NCAB manufacturing issues

  • European (Macedonia) vendor
  • ~10 days production time
  • Fault in the final step of the manufacturing process
  • Wrong parameters on the laser drilling of the microvias caused short circuits between layers
  • Even when following NCABs own design rules, the manufacturing process still failed
  • Second attempt succeeded
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Lessons learned

  • PCB manufacturing capabilities needed
  • Running dialog with layout designer and PCB manufacturer is vital
  • Dense and complex PCB, but in theory not difficult to produce
  • Even fairly conservative designs can fail
  • The HDI standard is not yet standard
  • Each manufacturer have their own processes
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Conclusion

  • The HDI process is under development
  • Close cooperation between schematic designer, layout designer and PCB

manufacturer is needed to decrease cost and improve reliability

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Recommended reading

  • The HDI Handbook - Happy Holden et. al
  • HDI Webinars - Wurth
  • BGA Breakouts and Routing - Charles Pfeil
  • HDI Design Guidelines - NCAB
  • HDI Layer Stackups for Large Dense PCBs - Happy Holden & Charles Pfeil
  • IPC-2226 and other HDI related IPC standards
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0.5mm, 0.4mm, 0.3mm...

0.4mm is becoming more and more common, with 0.3mm on the horizon

(0.3mm already used in telecom industry...)

0402 footprint ->

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Smartphone trend

Iphone 1 (2007) Iphone X (2018)

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Sources

  • Unfilled via-in-pads: http://www.ti.com/lit/an/spraav1b/spraav1b.pdf
  • PTH vs Microvia: https://www.eetimes.com/author.asp?section_id=36&doc_id=1320862
  • Iphone 1 vs Iphone X: https://www.idownloadblog.com/2017/11/03/gallery-iphone-x-original-iphone/
  • 0.3mm BGA pitch: https://www.hotwires.net/?tag=0-3mm-bga
  • Wurth HDI Design Guidelines: https://www.we-
  • nline.com/web/en/index.php/show/media/04_leiterplatte/2017_2/dg_poster_2/170125_WE_DesignGuide_HDI_Poster_EN_web.pdf
  • Microvia image: https://www.lpkfusa.com/products/microvia_drilling/
  • Via types: https://www.allpcb.com/pcb/vias.html
  • HDI in the Iphone X: https://www.macrumors.com/2017/11/02/fight-for-space-iphone-x/
  • A11 InFO stacked chip: https://wccftech.com/apple-a10-die-shots-chipworks-iphone-7/
  • Wurth HDI webinar series: https://www.we-
  • nline.com/web/en/leiterplatten/webinare/archiv/microvia_hdi_webinar/webinar_archiv_16.php
  • HDI PCB manufacturing: https://www.kfquickpcb.com/hdi-pcb/hdi-printed-circuit-boards.html
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Qu e stion s?

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w w w .rd -d a ta re sp on s.n o

A smarter solution starts from inside

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