[PPT] - Generalized Pattern Matching Micro-Engine Yuanwei Fang*, Raihan PowerPoint Presentation

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Generalized Pattern Matching Micro-Engine

Yuanwei Fang*, Raihan Rasool‡, Dilip Vasudevan*, Andrew A. Chien*† University of Chicago * Argonne National Laboratory† King Faisal University‡

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Big Data Applications

Deep Packet Inspection
Bioinformatics (DNA Alignment)
JSON/XML Parsing
Signal Triggering

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Deep Packet Inspection

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High speed network : 100Gb/s Growing number of patterns: 6000 Snort Rules Speed requirement: > 75 Tera DFAops/s Power budget : 200 W Energy efficiency requirement: > 375Gops/J

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Bioinformatics (DNA Alignment)

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Genome size： 130G base pairs Bioinformatics database: millions of species Speed requirement: > 1 Tera DFAops/s Power budget : 200 W Energy efficiency requirement: > 5 Gops/J

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Deterministic Finite Automata (DFA)

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Programmable Approaches

Intel Xeon E5-2600: 17G DFAops/second with 130W, 0.13Gops/J ;

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target

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Approach

Workload

M input characters(M DFA transitions) N DFA rules perform on the M input characters

Goal

Compute N x M transitions efficiently

Approach

Parallelize DFA execution Fused Instruction

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What Is Micro-Engine

Generalized Pattern Matching Micro-Engine ( GenPM ) is one micro-engine of 10x10 approach

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Basic RISC CPU

I-Cache

Micro- engine 2

I-Cache

Micro- engine 3

I-Cache

Micro- engine 4

I-Cache

GenPM

I-Cache

Micro- engine 7

I-Cache

Micro- engine 6

I-Cache

Micro- engine 8

I-Cache

Shared L1 Data Cache Local Memory

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GenPM Micro Architecture

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Fused Instructions: Multi-Step

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A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State

Acc_Vec

address

Accept

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Fused Instructions: Multi-Step

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A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

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Fused Instructions: Multi-Step

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A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

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Fused Instructions: Multi-Step

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A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

A D Q1 Q4 ENB

Current State

ALU

Local Mem

c b a

String buffer

Next State 1

Acc_Vec

address

Accept

Acc_Vec

CHECK

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Parallel DFA: Vector Instruction

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SSE ADD + + + + + + +

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Parallel DFA: Vector Instruction

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GMVSNEXT DFAop DFAop DFAop DFAop DFAop DFAop DFAop

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GenPM Code Example

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Data movement Multi-step parallel DFA execution Find precise matching position

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Methodology

Design space: Parallelism and step length
Baseline
32-bit 6-stage in-order RISC
4GB DDR3 DRAM
32KB L1 I-cache, 24KB L1 D-cache, 512KB L2 (modeled on Intel Silverthorne)
GenPM
1MB Local memory (up to 64 banks)
Vector and Fused Instructions
Performance/Power Model
Core : 32nm synthesis by Synopsys Processor Designer
Memories : MARSSX86/CACTI 6 + DRAMSim2
Workload
64 Snort rules from 2.9.5.6 snapshot, 10KB random network dump

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Performance

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36 243 300

289 1947 2498

500 1000 1500 2000 2500 3000

1 8 16

speedup versus RISC step length

Speedup

GenPM_8way GenPM_64way

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Energy Efficiency

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31 151 174 213 861 980

200 400 600 800 1000 1200

1 8 16

energy improvement versus RISC

step length

GenPM_8way GenPM_64way

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Throughput/watt (absolute)

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5 10 15 20 25 30 35 40

1 8 16

Throughput per watt(Gops/J) step length

Throughput/watt

GenPM_8way GenPM_64way

Scale to a 75W chip, GenPM delivers > 2.6 Tera DFAops/second

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Energy Breakdown

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0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

RISC GenPM_8B_1S GenPM_8B_8S GenPM_8B_16S GenPM_64B_1S GenPM_64B_8S GenPM_64B_16S

total energy LM L1_I L1_D L2 DRAM Core

LM_max = 83%

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General Comparison

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Related Work

ASIC: [Brodie, et.al. ISCA 2006], [Titanic System RXP], [ Cisco SCE ] FPGA: [Yang Xu, et.al. ANCS 2011], [ T Song, et.al. INFOCOM 2008], [I Sourdis et.al. VLSI 2008] CPU: [Mytkowicz et.al. ASPLOS 2014 ] , [ Intel HyperScan] GPU: [Vasiliadis G, et.al. CCS 2011], [ Lin CH, et.al. INFOCOM 2012] SoC: [C Johnson et.al. ISSCC 2010 ], [ Cavium Octeon ], [ IBM PowerEN ]

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Summery

GenPM is a high performance and energy efficient accelerator for

pattern matching workloads

ISA exploits parallelism and multi-step execution
Scale to a 75W chip, GenPM delivers > 2.6 Tera DFAops/second
GenPM approaches ASIC efficiency and integrates it into a

programmable core

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Future Work

DFA table compression
Scale up with multiple GenPM micro-engines
Explore more applications

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Acknowledgements

Defense Advanced Research Projects Agency (DARPA)
Agilent Technologies (now Keysight Technologies)
Synopsys Academic program
Dr. Tung Hoang and members of the Large Scale

Systems Group in the Department of Computer Science

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