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from atoms to systems www.tyndall.ie Nanotechnology Designed for - - PowerPoint PPT Presentation

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CHIST-ERA Conference 2011, 5 th -6 th September, Cork Nanotechnology Designed for Energy-Sustainable Electronics Giorgos Fagas Electronics Theory Group Georgios.Fagas@tyndall.ie from atoms to systems www.tyndall.ie

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CHIST-ERA Conference 2011, 5th-6th September, Cork

Nanotechnology Designed for Energy-Sustainable Electronics

Giorgos Fagas

Electronics Theory Group

Georgios.Fagas@tyndall.ie

“from… atoms to… systems”

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Nanotechnology Designed for Energy-Sustainable Electronics

Agenda

the Grand challenge (or… why are we here? )

 Energy consumption on the rise  Consumer electronics

  • pportunities for ICT (or…

what can we do? )

 Low-power (autonomous) devices (More-Moore)  Devices for energy efficiency (More-than-Moore)

a nano-inspired bottom-up approach (or… why nanotechnology? )

 From atoms to materials to devices  more Moore: ideal sub-threshold slopes at the nanoscale  more than Moore: nanomaterials for energy harvesting

expected impact (or… what are the outputs?)

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Nanotechnology Designed for Energy-Sustainable Electronics the Grand challenge

  • pportunities for ICT

a nano-inspired bottom-up approach expected impact

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www.tyndall.ie ICT and consumer electronics account for approximately 15%

  • f global

residential electricity consumption

Data: IEA report (2009)

ICT energy pie grows fast!

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1,700 TWh in two decades!

4,344 TWh 3,457 TWh 1,038 TWh

Maps: http://en.wikipedia.org Data: IEA report (2010)

By 2030, energy use by household ICT and consumer electronics will triple consuming 1,700TWh

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Nanotechnology Designed for Energy-Sustainable Electronics the Grand challenge

  • pportunities for ICT

a nano-inspired bottom-up approach

  • Co-design of nanotechnology-enhanced ICT

expected impact

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Technology Booster 1 Elements used in Chip Fabrication

Courtesy J.-P. Colinge

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A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors

  • T. Ghani et al, IEDM 2003, p. 978

nMOS: tensile strain pMOS: compressive strain

Technology Booster 2 Mobility enhancement by strain

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Gate Source Drain Buried oxide Back gate (substrate)

Source Drain Gate

ID

Buried oxide

20 nm

Polysilicon Gate

Silicon Fin

Buried Oxide

Gate Source Drain BOX

–Gate –Gate

“1 Gate” “1 Gate” “2 Gates” “2 Gates” “3 Gates” “3 Gates”

Technology Booster 3 Evolution of Transistors Geometry

“Gate-all-Around” “Gate-all-Around”

Courtesy J.-P. Colinge

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Transistor scaling

why nanowires?

Intel 22nm Ivy Bridge (2011)

  • R. S. Chau,

Technology@Intel Magazine (2006)

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Si Ge

Energy Scavengers Micro-fluidics Integrated Sensors Logics and Transmittance NW modified CMOS module NW modified CMOS module CMOS module

I O Semiconducting Nanowire Platform for Autonomous Sensors

SiNAPS

SiNAPS mote concept (see www.sinaps-fet.eu)

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Nanoelectronics meets atomic design

Ma et al, Science 299, 1876 (2003) Sing et al, IEEE TED 55, 3107 (2008)

Top-down Bottom-up

size convergence with atomic-scale modelling

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R.W. Dutton and A.J Strojwas, IEEE Trans. CAD of ICS 19, 1544 (2000)

TCAD tools hierarchy

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Co-design of nanotechnology-enhanced ICT

a-priori technology evaluation and design Photonics Micro/Nano electronics Energy harvesting Materials research Device modelling TCAD Atomic-scale fundamentals

Design for manufacturing, circuit models New designs, architectures, and materials IV & III-V nanomaterials, alloys, functional oxides

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Nanotechnology Designed for Energy-Sustainable Electronics the Grand challenge

  • pportunities for ICT

a nano-inspired bottom-up approach

  • Example 1: ideal sub-threshold slopes at the

nanoscale

expected impact

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x x Junctionless transistor

Gated Resistor (or CMOS without junctions)  no doping gradients The cross-section of the channel is small enough that gate can deplete the heavily doped channel (8 x 1019 cm-3) entirely, hence can turn off device

J-.P. Colinge et al, Nat. Nanotech. 5, 225 (2010)

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x x Junctionless transistor characteristics

J-.P. Colinge et al, Nat. Nanotech. 5, 225 (2010)

new devices show even smaller short channel effects

 

D G

I d dV SS log 

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“Short channel” (35nm) “Ultrashort channel” (<10nm)

L L?

“Junctionless” “Junctionless”

Dopant profile issue

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Mulliken population analysis

localization radius of the dopant electron or hole is ~ 1.5 nm

Dopants in nanowires

fundamental limitation for junctions

Position of doping atoms

ΔQ = Qn-type - Qintrinsic at Vg = 0 V

wire axis (Å)

  • L. Ansari, B. Feldman, G. Fagas, J-.P. Colinge, and J. C. Greer,
  • Appl. Phys. Lett. 97, 062105 (2010)
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x x (Junctionless) transistor scaling Using realistic electronic structure, can the device scale down to sub-5nm?

  • Classical device simulation

C.W. Lee et al, Appl. Phys. Lett. 94, 053511 (2009)

  • Experimental device

J-.P. Colinge et al, Nature Nanotech. 5, 225 (2010)

  • Geometry dependence in classical and

quantum devices

  • P. Razavi et al, submitted (2011)

Gate length Lg > 10nm

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p-type (Ga doped) 8 x 1020 cm-3

Transistor behaviour at 3nm

  • L. Ansari, B. Feldman, G. Fagas, J-.P. Colinge, and J. C. Greer,
  • Appl. Phys. Lett. 97, 062105 (2010)
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  • L. Ansari, B. Feldman, G. Fagas, J-.P. Colinge, and J. C. Greer,
  • Sol. Stat. Elec. (2011)

Subthreshold slope

~ 80 mV /decade  near to theoretical limit!

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Si and CNT JL transistors

comparison

  • L. Ansari et al, in preparation

– 5.4 nm

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Nanotechnology Designed for Energy-Sustainable Electronics the Grand challenge

  • pportunities for ICT

a nano-inspired bottom-up approach

  • Example 2: nanomaterials for energy harvesting

expected impact

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Energy harvesting possibilities Ambient energy

Battery

  • perated

systems

  • R. J. M. Vullers, Zero-Power ICT Workshop 2009
  • R. J. M. Vullers et al, Solid-State Elec.53, 684 (2009)
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  • V. Sivakov, G. Andrä, A. Gawlik, A. Berger, J. Plentz, F. Falk, S.H. Christiansen, Nano Lett. 9, 1549 (2009)

Axial junctions in nanowire arrays

antireflection effect in NW arrays

up to 4.4% efficiency under 1-sun illumination

p+ n n+

http://en.wikipedia.org

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Arrays of nanowire coaxial cables

  • 1,2 -1,0 -0,8 -0,6 -0,4 -0,2 0,0 0,2 0,4 0,6 0,8 1,0
  • 30
  • 20
  • 10

10 20 30 40 50 60 70 80

Current density (mA/cm

2)

Voltage (V)

AM 1.5 Dark

Contact area: 7.02 mm

2

Efficiency: 7.29% Open circuit voltage: 476 mV Current density: 27.03 mA/cm

2

Filling factor: 0.562

Guobin Jia, Martin Steglich, Ingo Sill, and Fritz Falk (IPHT), 2011

a b c d 500nm 500nm 500nm 500nm

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Towards miniaturisation

Erik Garnett and Peidong Yang, Nano Lett. 10, 1082 (2010)

robust performance against thin film solar cells

PV technology platform sets poly-Si thickness <100µm in 2030

8µm thick Si absorber 20µm thick Si absorber Efficiency: 4.83%

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Atomic structure of a-Si (a-Si:H)

  • M. Legesse, M. Nolan and G. Fagas, unpublished

heat and quench MD method for structure generation

  • K. Laaziri et al,

PRB 60, 13520 (1999)

radial distribution function a-Si cell of 512 atoms

melt at 3500K – quench at 300K

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Electronic properties of hydrogenated a-Si

log of DOS vs energy (eV) for aSi:H (12%H)

  • M. Legesse, M. Nolan and G. Fagas, unpublished

D.V. Lang et al, PRB 25, 5285 (1982)

first-principles experiment

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Ba distorts the structure, reducing Cu-Cu interactions and increasing the transparency to visible light. By contrast, other dopants reduce the transparency.

Challenge: A p-type transparent conducting oxide (TCO) for transparent electronics. Question Posed: Can we use modelling to design a new p-type TCO instead of traditional trial- and-error approach? Results: Predicted a novel TCO, with optimal composition for transparency: Ba-doped SrCu2O2. Experiments by European partners confirmed its properties. Material was licensed to Umicore and patented.

New materials for transparent electronics

CRYSTAL STRUCTURE OF Ba-doped SrCu2O2; blue=Ba, green=Sr, pink=Cu, red=O. SCHEMATIC ELECTRONIC STRUCTURE showing gap between conduction band and Cu-derived valence band more transparent to visible light doping widens band gap SrCu2O2 Ba-doped SrCu2O2

  • M. Nolan & S. D. Elliott, Chem. Mater. 20, 5522 (2008)
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Nanotechnology Designed for Energy-Sustainable Electronics the Grand challenge

  • pportunities for ICT

a nano-inspired bottom-up approach expected impact

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A modelling hierarchy for nano-inspired bottom-up technology design

  • Customer Need
  • Process S

imulation

  • Device Modelling
  • Parameter Extraction
  • Compact Models
  • Circuit S

imulation

30%-40% cost reduction

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Impact of nanotechnology designed for ICT

Science, Technology and Innovation Nanotechnology Computer Aided Design

Enterprise, Innovation and Industry Growth

Outputs: a priori technology evaluation and design More Moore, More than Moore, Beyond Moore

Atomic scale fundamentals Materials research Device modelling

Communications Energy Health Environment

Outputs: Low-power processing and communications Point-of-care diagnostics, body sensor network Pollution monitoring, traffic control ICT device autonomy

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Acknowledgments

Lida Ansari (Tyndall, ETG) Prof Jean-Pierre Colinge (Tyndall, Micro/ nano-electronics centre) Prof Fritz Falk (IPHT) Dr Baruch Feldman (Weizmann Institute) Prof Jim Greer (Tyndall, ETG director) Marios Iakovidis (Tyndall, ETG) Merid Legesse (Tyndall, ETG) Dr Philip Murphy-Armando (Tyndall, CMT group) Dr Michael Nolan (Tyndall, ETG) Pedram Razavi (Tyndall, US D group) Dr S adasivan S hankar (INTEL S anta Clara, Materials Modeling group)

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Thank you! Q&A