FIR Filter Design, Implement, and FIR Filter Design, Implement, and - - PowerPoint PPT Presentation

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FIR Filter Design, Implement, and FIR Filter Design, Implement, and Applicate on Audio Equalizing System Applicate on Audio Equalizing System

~ ~System Architecture System Architecture Instructor: Prof. Andy Wu 2004/10/21

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Review of DSP System Review of DSP System

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Basic Structure for Audio System Basic Structure for Audio System

Use a timer interrupt to generate a periodic event. Once interrupt, its handler should:

Reset the counter of timer and keep timer active Generate an invoking signal to get a datum from ADC Use the datum in DSP algorithm Put the computation result to DAC and activate a conversion

Sampling frequency is set by the number which timer counts and generates interrupt.

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Control Mechanism Control Mechanism

Use DMA controller for input buffer and output buffer. Use SPI to control ADC behavior Use SPORT to transmit data with peripheral devices Cycle time:

ADC response time DAC response time Time to execute DSP algorithm Time to execute other parts (egg. Key manipulation)

What will happen if latency is greater than cycle time?

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System State Diagram System State Diagram

Can be implement through:

Infinite looping in main() and polling peripheral devices Infinite looping in main() with event-driven interrupt service routine

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Review: Program Sequencer Review: Program Sequencer

Core Architecture Typical Program Flow Variations

[3]

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Review: Core Event Controller & Review: Core Event Controller & System Interrupt Controller System Interrupt Controller

The mechanism to call Interrupt Service Routine (ISR) is implement with two hardware block in BF533 chip:

CEC and SIC

Core Event Controller (CEC)

The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events. The two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software interrupt handlers. Preserve seven prioritized interrupt inputs to support peripherals.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and routing

• f events from the many peripheral interrupt sources to the

prioritized general-purpose interrupt inputs of the CEC. Provide a default mapping, but user can alter the mappings and priorities of interrupt events by writing the appropriate values into the Interrupt Assignment Registers (SIC_IARx)

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System ISR Flow Chart System ISR Flow Chart

Logs request and keep track of system interrupt serviced or not Check whether wake up core

• r not

Mapping peripheral interrupt to core interrupt, determine interrupt priority Latch not serviced interrupt Look up EVT by entry to find the entry point of interrupt service routine MMR is programmable Keep track of all currently nested interrupt to determine which

• ne to serve

[3] [1]

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System Interrupt Controller System Interrupt Controller

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System Interrupt Controller (cont.) System Interrupt Controller (cont.)

Set the relative priority of peripheral interrupts by mapping them to appropriate general-purpose interrupt level in the core

Core Event Controller

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Core Event Controller Core Event Controller

Keep iteration to handle and track nested interrupts Priority mapping and ISR routing Event Vector Table (EVT) Interrupt Service Routine (ISR)

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Register Event Handler Register Event Handler

The register_handler function determines how the hardware event kind is handled by registering the function pointed to by fn as a handler for the event. Synopsis

#include <sys/exception.h> ex_handler_fn register_handler(interrupt_kind kind, ex_handler_fn fn);

ex_handler_fn value: The kind event is an enumeration identifying each of the hardware events—interrupts and exceptions—accepted by the Blackfin processor.

typedef enum { ik_emulation, ik_reset, ik_nmi, ik_exception, ik_global_int_enable, ik_hardware_err, ik_timer, ik_ivg7, ik_ivg8, ik_ivg9, ik_ivg10, ik_ivg11, ik_ivg12, ik_ivg13, ik_ivg14, ik_ivg15 } interrupt_kind;

[1]

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ISR with Compiler Macro ISR with Compiler Macro

Include sys/exception.h to define a function as ISR. Declared and defined using macros in this header: There is a macro for each of the three kinds of events the compiler supports:

EX_INTERRUPT_HANDLER, EX_EXCEPTION_HANDLER, EX_NMI_HANDLER

Declare and define MyIsr() to be a handler for interrupt-type events.

#include <sys/exception.h> EX_INTERRUPT_HANDLER(MyIsr) {…}

By default, the ISRs generated by the compiler are not re-entrant. There is a different macro for specifying a re-entrant interrupt handler:

EX_REENTRANT_HANDLER

The EX_INTERRUPT_HANDLER() macro uses a generic pragma, #pragma interrupt, to indicate which function is to be an interrupt

• handler. This generic pragma does not indicate which interrupt the

function will handle.

For more detail information about how compiler implements ISR and other functions available in ISR, please check Reference [4].

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ADSP BF533 EZ ADSP BF533 EZ-

• KIT Block Diagram

KIT Block Diagram

[2]

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Introduction to Audio CODEC: AD1836 Introduction to Audio CODEC: AD1836

Include 4 ADC and 6 DAC

3 channels of stereo audio output 2 input channels with max analog to digital conversion rate: 96KHz

Use SPORT interface to communicate with uP, and support:

I2S mode transmission

Maximum sampling rate: 96KHz Constrained output: 2 channels

Time-Division Multiplexed (TDM) mode transmission

Maximum sampling rate: 48KHz Allow simultaneous use of all input and output

Enable: Push Button Enable Switch (SW9) on p3-10

Configured through SPI port of uP BF533 More configuration setting of AD1836, please check reference [5]

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AD1836 on BF533 EZ AD1836 on BF533 EZ-

• KIT EVBoard

KIT EVBoard

• Hardware Reset
• Initialization through SPI
• Data communication through SPORT

[4] [5]

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SPI Controller in BF533 SPI Controller in BF533

Serial Peripheral Interface (SPI) compatible port controller Industry-standard synchronous serial link (4 wire) for multimaster multislave communication

SCK : serial peripheral interface click signal SPISS : serial peripheral interface slave select input MOSI : master out slave in MISO : master in slave out

On-chip IO interface for connection between:

Other CPU or microcontrollers Codec ADC or DAC SP/DIF or AES/EBU digital audio transmitters and receivers LCD displays Shift registers FPGAs with SPI emulation

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Setting SPI Controller Setting SPI Controller

Register based control mechanism

SPI_BAUD setting baud rate, 0 or 1 will disable SPI : assign 16 SPI_CTL configure and enable SPI SPI_FLAG slave-select mapping flag : PF4 is CS of AD1836 SPI_STAT detecting transmission complete or fail SPI_TDBR transmit data buffer register SPI_RDBR receive data buffer register SPI_SHADOW for debugging, a shadow of SPI_RDBR

Set SPI control registers before communicate with AD1836 Store the configuration data in array, use DMA transfer to communicate with AD1836 Check reference datasheet of AD1836 for detail understanding

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SPI_CTL SPI_CTL

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SPORT Controller SPORT Controller

Synchronous Serial PORT controller, support a variety of serial data communication protocols. Capable for full-duplex operation Use 8 wire

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SPORT Block Diagram SPORT Block Diagram

On-chip Block diagram of SPORT0 and SPORT1 Interconnection between uP and codec

[3]

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SPORT Control Mechanism SPORT Control Mechanism

Each SPORT has its own set of control register and data buffers. Before enable SPORT controller, it should be configured by setting bit and field value in configuration register:

SPORTx_TCR1, SPORTx_TCR2 SPORTx_RCR1, SPORTx_RCR2 Once enabled, further write to those configuration register is ignored, except SPORTx_TCLKDIV, SPORTx_RCLKDIV, and multichannel mode channel select registers. TSPEN and RSPEN bit control enable or not

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Setting SPORT Controller Setting SPORT Controller

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Setting SPORT Controller Setting SPORT Controller

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Setting SPORT Controller Setting SPORT Controller

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Setting SPORT Controller Setting SPORT Controller

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Exercise Lab Exercise Lab

Example code @

/Analog Devices/VisualDSP 3.5 16-Bit/Blackfin/EZ-KitsADSP-BF533/ Examples/Audio codec talkthrough/C/I2S/

Read readme.txt first and then trace the source code Build and Run Receive analog audio signal from PC phone jack. Connect output phone jack on EZ-KIT to Speaker Playback any music file and listen

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Submission Submission

Due: 2004/11/04 Thursday Mailto: tommy@access.ee.ntu.edu.tw Requirement:

Observe the example system, draw detailed state- diagrams of each part Plot input and output signal for a period of time and compare Discussion Suggest to this slide: content, teaching skill… anything you feel inadequate.

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Reference Reference

[1] “Visual DSP++ 3.5 Help for 16-Bit Processors”, ~/VisualDSP 3.5 16-Bit/Help/vdsp-help.chm [2] “ADSP-BF533 EZ-KIT Lite Evaluation System Manual”, ~/VisualDSP 3.5 16-Bit/Help/WmBF533.chm [3] “ADSP-BF533 Blackfin Processor Hardware Reference” ~/VisualDSP 3.5 16-Bit/Help/BF533_hwr_101.chm [4] “Visual DSP++ 3.5 Compiler and Library Manual for Blackfin Processors”, Revision 2.2, October 2003, Part Number 82-000410-03, p.1-154~1-160 [5] “Multichannel 96 kHz Codec AD1836A datasheet”, http://www.analog.com/UploadedFiles/Data_Sheets/802651676AD1836A_0.pdf