Exploring Benefits and Designs of Optically Connected Disintegrated - - PowerPoint PPT Presentation

Exploring Benefits and Designs of Optically Connected Disintegrated Processor Architecture

Yan Pan, Yigit Demir, Nikos Hardavellas, John Kim!, Gokhan Memik

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Motivation

Transistor density grows exponentially But, processors are physically constrained

– Low yield, bandwidth wall, power wall – Dark silicon: we can build dense devices we cannot afford to power

Optically-Connected Disintegrated Processor

(OCDP)

– Divide (impractical) monolithic processor into chiplets – Improves yield – Breaks the bandwidth wall – Breaks the power wall

• Spread out chiplets, cheaper cooling

Motivation

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Motivation

Advantage of nanophotonics

– Latency – Bandwidth density

Using nanophotonics for inter-chip interconnect

– Reduced memory latency – Increased off-chip bandwidth – Increased total chip area – Increased power budget

Analytical model* for performance estimation

* N. Hardavellas et al., Tech Report NWU-EECS-10-05, Mar. 2010. Motivation

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Memory Latency

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Motivation

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Off-chip Bandwidth

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Motivation

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Scaling Power, Chip Area

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Motivation

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Motivation

Performance impact

– Reduced memory latency minimal – Improved off-chip bandwidth small – Total chip area small – Power budget big

Power budget scalability is critical

– Spread out chiplets – Cheaper cooling

Optically-Connected Disintegrated Processor

(OCDP)

Motivation

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Off-chip Optical Channels

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Optical fiber is low-loss, high speed

– Enables further spreading out chiplets – BW density was a challenge

*

* J. Cardenas et al., Optics Express 2009 Motivation

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Dense Off-chip Coupling

Dense optical fiber array [Lee et al., OSA/OFC/NFOEC 2010] <1dB loss, 8 Tbps/mm demonstrated

Motivation

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OCDP Design Considerations

Inter-chiplet optical channel technology

– Optic fiber for low loss

Inter-chiplet optical channel organization

– Point-to-point [Koka et al., ISCA 2010] – Minimize waveguide and coupler loss

On-chip topology

– Scalable chiplet size

On-chip / off-chip bandwidth interfacing

– Distributed BW, seamless integration

Motivation

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OCDP Architecture

Chiplet 1 Chiplet 0 src Chiplet 3 Chiplet 2 Chiplet 4 Cross-chiplet assemblies share an optical bus, forming optical crossbars (FlexiShare) Chiplet 0 Chiplet 3 Laser Source couplers Optical fiber Electrical cluster dst

OCDP Arch.

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Firefly On-chip Topology

Firefly on-chip topology [Pan et al., ISCA 2009]

– Flexible chiplet sizing, optical on-chip communication

FlexiShare optical crossbars [Pan et al., HPCA 2010]

– Flexible bandwidth provisioning – Light-weight optical arbitration needed, proposed

Chiplet 0

C0R3

P P P P

C0R0

P P P P

C0R2

P P P P

C0R1

P P P P

C2R0

P P P P

C3R0

P P P P

C1R0

P P P P

C0 C1 C2 C3

C0R3

P P P P

C0R0

P P P P

C0R2

P P P P

C0R1

P P P P

C0

... ... C2R0

P P P P

C3R0

P P P P

C1R0

P P P P

C1 C2 C3

... ... ... ... A0 A1 A2 A3

FlexiShare CH0 CH1 CHM-1 ... R0 R1 Rk-1 R0 R1 Rk-1 ... ... ... ... ... ...

• ut
• ut
• ut

in in in OCDP Arch.

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Extending across chiplets

Distributed bandwidth across chiplets Flexible inter-chiplet bandwidth provisioning Minimal number of couplers Seamless on-chip/off-chip interfacing

Chiplet 0 Chiplet 1

OCDP Arch.

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Technology Assumptions

Moderate DWDM (16-way)

Parameter Loss Parameter Value Coupler 1 dB Detector Sensitivity 0.01 mW Splitters 1 dB DWDM 16 ! Non-linear 1 dB fiber coupler loss 0.1 Modulator Insertion 0.1 dB fiber loss 2.00E-06 dB/cm Waveguide 0.3 dB/cm ring heating power 40 uW/ring Ring Through 0.001 dB Modulation Power 80 fJ/bit Filter Drop 1.5 dB Demodulation Power 40 fJ/bit PhotoDetector 0.1 dB

Power Eval.

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Optical Power (320-core)

5-chiplet OCDP vs. single-chip topologies Total number of optical channels (wavelengths)

held constant.

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Power Eval.

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Per-Core Network Static Power

~ 30% power reduction compared to the best

alternative.

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Power Eval.

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Scaling Up

OCDP limits the total on-chip waveguide length Better optical scalability ! " #! #" $! $" %! %" &! &" '()* +*",-%$!. '()* +*",-#$/!. 0123456 +(7/,-#$/!. 053819:;23 +-#$/!. '()* +*<,-$%!&. '()* +*#=,-&%"$.

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Power Eval.

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Scaling Up

OCDP shows very good power scalability. Single-chip is impractical for 1280-core

processor

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Power Eval.

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Conclusion

OCDP leverages

– Low latency / high bandwidth density – Low loss optic fibers

Power scalability is critical

– Minimize optical loss on the path

Seamless on-chip / off-chip interfacing

– Firefly intra-chiplet (distributed off-chiplet BW) – Point-to-point (Dragonfly) inter-chiplet

Performance evaluation needed Chiplet composition to be explored

Conclusion

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On-chip Optical Channel

Silicon photonics with DWDM

(Offchip) Laser Source Waveguide Resonant Modulators Electrical Signal Electrical Signal Filters Photo Detector

Motivation

(off-chip)