Electronics modules & DAQ system IGARASHI Youichi 1. - - PowerPoint PPT Presentation

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Electronics modules & DAQ system IGARASHI Youichi 1. - - PowerPoint PPT Presentation

May 09, 2023 184 likes •447 views

Electronics modules & DAQ system IGARASHI Youichi 1. Front-end studies COLLABORATION KEK online/electronics group 2. Read-out platform Belle DAQ group 3. Back-end system KEK Neutrino DAQ group Hiroshima Institute of Technology 4.

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SLIDE 1

Electronics modules & DAQ system

IGARASHI Youichi

1. Front-end studies 2. Read-out platform 3. Back-end system 4. Signal handling 5. Summary

COLLABORATION KEK online/electronics group Belle DAQ group KEK Neutrino DAQ group Hiroshima Institute of Technology University of Hawaii University Tokyo BINP(Budker Institute of Nuclear Physics) KRAKOW Institute of Nuclear Physics Densan Co. Ltd. Designtech Co. Ltd

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SLIDE 2

Requirements of electronics systems for J-PARC experiments

  • T

r i g g e r : 数 K H z

  • D

a t a f l

  • w

: 数十 M B / s e c

  • 保守コ

スト の削減

– C u s t

  • m

i z e / d e v e l

  • p

m e n t / u p g r a d e

  • 使用にあまり

特別な知識を要し ない。

  • 過去の資産と

の共存。

消費電力が大き い、 新規モジュ ールの入手が出来ない。 FastBus ほと んどディ ジタ ル回路専用、 アナログ信号を扱う のが難 し い(負電源、 電源のノ イ ズ) VME Compact PCI ~300 µsec 以上の dead-time、 保守コ スト が高い。 TKO あまり 速度が出ない、 チャ ンネル密度が上がら ない。 CAMAC

New front-end system.

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SLIDE 3

Front-End Studies

  • Required Readout System

– General (DC, MWPC,…)

  • Timing resolution : ~1nsec
  • Analog dynamic range <12 bit

– Wide dynamic range waveform sampling (CsI(Tl),…)

  • Timing resolution : A few hundred nsec
  • Analog dynamic range : 16~18bit
  • Wave form sampling

– High timing resolution (TOF)

  • Timing resolution : <50 psec

– High density device

  • Silicon micro-strip detector
  • Multi-anode PMT
  • TMC + ADC
  • Waveform sampler

Multi Stage Amp + Flash ADC

  • VA-TA + Flash ADC
  • New Front-end ASIC

High-resolution TMC

Time-stretcher + TMC

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SLIDE 4

TMC (Time Memory Cell)

  • L
  • g

i c c e l l d e l a y を利用 し た時間測定。

– A T L A S 用に開発さ れた A M T 2 , A M T 3 が入手可能 – K E K 回路グループでも 開発/ 試作中

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SLIDE 5

TMC/ADC multi-function device

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SLIDE 6

TMC/ ADC specification

TDC, ADC Input < ? mW/chip Power dissipation 2 V Analog input range 8 bit < <10 bit ADC resolution < 22MHz selectable SysCLK/N (N=2,4,8) ADC sampling rate < 45MHz System clock 3.3～5V Power supply 256 depth (Depth is changed by CSR) L1 buffer depth 0.5～2nsec TMC timing resolution 8 ch/chip # of channels (ch/chip)

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SLIDE 7

Wide dynamic range waveform sampling

  • ASIC Multi Stage Op-amp

– ~18bit / dt~200nsec

Pipeline Buffer x4 x4 x4

Post AMP

x4

Comparator x256 x64 x16 x4

FADC

Signal

x1

  • utput

input

KEK回路グループで開発/試作中

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SLIDE 8

High density devices

  • ideas VA-TA

– Amp/shaper – Sample & hold – Analog serializer

  • Channel to time converter

5 4 3

Time Ch.

5 4 3 2 1

Time

  • B

E L L E S V D 2 , K 2 K S c i b a r 検出 器で使用中

  • よりD

e a d

  • t

i m e の少ないも のを A S I C で生産でき るよう に研究中

2 1

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SLIDE 9

Analog Memory Cell (AMC)

KEK回路グループで開発/試作中

高速ク ロッ ク なし で1GHz waveform sample が可能

(For PMT, Drift chamber)

特徴

  • 低コ

スト

  • 低消費電力
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SLIDE 10

Read-out Module design Concept

  • Working under 10kHz trigger

– Front-end Buffering

  • Waiting trigger decision
  • Buffering trigger non-uniform timing
  • Buffering behind non real-time system

– On-board data reduction

  • Wide scalability

– From small test experiments to large experiments such as Super KEKB experiment

  • Modular system

– Maintenance, upgrading, developing

  • Using standard and commercially available technologies

– Easy to follow evolution of technology – Cost effectiveness

  • Production, maintenance, upgrading
  • High channel density : ~100 ch/board
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SLIDE 11

Read-out module (COPPER)

  • 9U euro card(VME)
  • 4 Front-end A/D

card slot

  • Processor PMC slot
  • Trigger module slot
  • general PMC slot
  • VME-32 interface
  • 1MB x 4 FIFO
  • 32bit 33MHz PCI

bus

  • 2 network interface

– Processor module – On-board NIC

A/D card slot A/D card slot A/D card slot A/D card slot Trigger module Slot (PMC) PMC slot PMC slot (Processor)

PCI (PMC) VME Network

KEK elec./online/BELLE DAQ group

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SLIDE 12

PCI / PMC

  • PCI Mezzanine Card,

IEEE1386.1

– PCI 互換 – さ まざまなモジュ ールが流 通し ている。

  • Processor (PPC/x86/…)
  • 100Base/Gigabit

Ethernet

  • IEEE1394
  • Memory
  • Etc….

Ramix PMC610 4port Ethernet card

PC architecture / Linux 2.4

  • 研究者がなじ

んでいる環境。

– 普段から 解析やメ ールで使用し ている。 – プログラ ムの開発に抵抗が少ない。 – その辺の PC で開発可能。

  • 商業的に成功し

ている

– 高速なプロセッ サを安く 購入でき る。 – アッ プグレード が期待でき る。

  • 複雑なデバイ

スをド ラ イ ブでき る。

  • いろ

いろ なノ ウハウが公開さ れている。

Radisys EPC-6315

  • 800 MHz Pentium IIIm Processor.
  • Up to 512 MB SDRAM with ECC.
  • 10/100 BaseT Ethernet port
  • On-board Compact Flash socket.
  • 32-bit 33/66 MHz PCI bus interface.
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SLIDE 13

Performance Test

  • Data size of this test

– 400B * 4 = 1600B

  • Basic speed of data

transfer during DMA cycle

– ~80MB/sec

  • The system works stably.
  • Performance limited by

processor speed.

– It can accept more high frequency trigger by more powerful processor.

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SLIDE 14

Front-end daughter card

Prototype of flash ADC

  • ADC: Analog Devices AD9235-20
  • Resolution: 12bit
  • Number of channel: 8
  • Max sampling clock: 40MHz

開発中の Front-end daughter card

  • Time Memory Cell (TMC) based pipeline TDC

– TMC : AMT3 – Input : 24ch LVDS – 96 ch/board – Resolution: 0.78 ns/bit

  • Flash ADC

– 8 b i t / 5 M H z s a m p l e 2 c h x 4 F A D C – 1 2 b i t / 6 5 M H z s a m p l e 8 c h x 4 F A D C

計画中の Front-end daughter card

  • CCD read-out ADC
  • Analog memory cell

– 1GHz sample

  • 16bit wave form sampler

– 5MHz sample

  • High resolution TDC

– 50psec

  • DSSD pipeline front-end (CMS)
  • Charge sensitive ADC

– Current integrator type – ASIC

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SLIDE 15

Read-out by CAMAC

  • TOYO CC/NET

– CAMAC crate controller equipped with built-in PC – High speed CAMAC ACTION (~1µsec) used by pipe-line architecture – Developed by TOYO/Fird/KEK online/elec. Gr. Built-in PC

  • PC104plus
  • Crusoe TM5400 500MHz
  • Memory 310MB
  • Fast Ethernet
  • Compact Flash
  • …
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SLIDE 16

Data way (Event Builder)

COPPER

VICTOR/VME-CPU SCH/SMP/VME-CPU

Network Serial interface (Network/USB/Firewire/Spacewire/…) Network base Event Builder

PC

CC/NET

PC Back-end PC

Network To Data server

TKO

Local Storage

CAMAC

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SLIDE 17

Signal handling tools

General purpose I/O module

  • NIM

– Traditional modules

  • KEK-VME (VME + extended power supply + low noise power supply)

– Read-out module (COPPER) – General purpose I/O module – Clock Generator – Gate Generator – Discriminator (under development) Gate Generator/Clock Generator

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SLIDE 18

Trigger Logic (VME)

COPPER COPPER Trigger distribution system

  • LVDS serial link
  • Trigger/Busy
  • Trigger ID
  • Trigger info.

Belle style

Trigger module

COPPER

CAMAC Trigger Logic (NIM/VME/KEK-VME) GONG

KEK-VME TKO Simple style

Trigger distribution

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SLIDE 19

まと め

  • K

E K

  • n

l i n e / e l e c t r

  • n

i c s g r . では共同研究者の人々 と 共にの次期実験のために以下のよう な開発を行っ ている。

– Front-end studies

  • TMC,TMC/ADC multi-function device
  • Multi-stage Amp.
  • VA-TA, New front-end device
  • Analog memory cell
  • ASIC technology

– Read-out system

  • Read-out platform COPPER
  • CAMAC C.C. CC/NET

– KEK-VME base signal handling modules – Back-end system

  • Network event builder
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SLIDE 20

Appendix

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SLIDE 21

Pin assignment of power supply connector (IEC 61076-4-101)

200A 320A 100A Total Max Current +3.3V

  • 3.3V
  • 5.0V

Voltage

GND C2 C1 GND S7- S7+ GND 19 GND S6- S6+ GND S5- S5+ GND 18 GND S4- S4+ GND S3- S3+ GND 17 GND S2- S2+ GND S1- S1+ GND 16 GND GND GND GND GND GND GND 15 GND

  • 5V
  • 5V
  • 5V
  • 5V
  • 5V

GND 14 GND GND GND GND GND GND GND 13 GND

  • 3.3V
  • 3.3V
  • 3.3V
  • 3.3V
  • 3.3V

GND 12 GND

  • 3.3V
  • 3.3V
  • 3.3V
  • 3.3V
  • 3.3V

GND 11 GND

  • 3.3V
  • 3.3V

GND GND GND GND 10 GND GND GND GND GND GND GND 9 GND GND GND GND GND GND GND 8 GND GND GND GND +3.3V +3.3V GND 7 GND +3.3V +3.3V +3.3V +3.3V +3.3V GND 6 GND +3.3V +3.3V +3.3V +3.3V +3.3V GND 5 GND +3.3V +3.3V +3.3V +3.3V +3.3V GND 4 GND GND GND GND GND GND GND 3 GND GND GND GND GND GND GND 2 GND GND GND GND GND GND GND 1 f e d c b a z Pos.

Form Factor and Power Supply

  • Euro card/crate

– Cost effectiveness – 9U and 6U – VME-32 bus

  • J0 Connector for

Power Supply

– To treat front-end analog-digital conversion devices

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SLIDE 22

Crate Form Factor

Front plug-in VME Physics Board 9U x 400D

9U 415.6 182.75

Front plug-in VME CPU Board 6U x160D Rear plug-in I/O Physics Board 6U x 160 PSU KEK 9U Custom VME Subrack Plan - Rev. 0.1 for High Energy Physics Experimentation (Shimada Aug.13,2002)

+5V,+3.3V,-5V,-3.3V,+12V,-12V

6U Custom VME backplane, with J1, J2 and JO connectors Side View 3U Optional backplane, for rear I/O Backplane rear stiffener rail

Extend Power Supply Connector +3.3V: 320A

  • 3.3V: 200A
  • 5V: 100A

VME 9U base

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SLIDE 23

KEK-VME crate and Read-out modules

COPPER/ FI NESSE(jig)/ EPC-6315/ PMC-memory

slide-24
SLIDE 24

ASI C Current I ntegrator

  • Bipolar 0.6µm
  • ft : 2~20 GHz

KEK electronics group

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SLIDE 25

Event Builder

  • Ethernet base event builder is works well under ~10 MB/sec data flow

condition.

  • We expect this system works well under ~50MB/sec data flow

condition by the layer tuning.

Belle Network Event Builder Configuration