Today… EECS 373 Design of Microprocessor-Based Systems Memory-Mapped I/O Example Bus with Memory-Mapped I/O Branden Ghena University of Michigan Bus Architectures AMBA APB Lecture 4: Memory-Mapped I/O, Bus Architectures September 11, 2014 Slides developed in part by Mark Brehob & Prabal Dutta 1 2 Memory-mapped I/O Memory-mapped I/O • Microcontrollers have many interesting • Instead of real memory, some addresses map to peripherals I/O devices instead – But how do you interact with them? Example: • Need to: • Address 0x80000004 is a General Purpose I/O (GPIO) Pin – Send commands – Writing a 1 to that address would turn it on – Configure device – Writing a 0 to that address would turn it off – Receive data – Reading at that address would return the value (1 or 0) • But we don’t want new processor instructions for everything – Actually, it would be great if the processor know anything weird was going on at all 3 4 Smartfusion Memory-mapped I/O Memory Map • Instead of real memory, some addresses map to I/O devices instead • But how do you make this happen? – MAGIC isn’t a bad guess, but not very helpful Let’s start by looking at how a memory bus works 5 6 1
Today… Bus terminology • Any given transaction have an “ initiator ” and “ target ” Memory-Mapped I/O • Any device capable of being an initiator is said to be a “ bus master ” Example Bus with Memory-Mapped I/O – In many cases there is only one bus master ( single master vs. multi-master ). Bus Architectures • A device that can only be a target is said to be a slave device. AMBA APB 7 8 Basic example Read transaction Let’s demonstrate a hypothetical example bus Initiator wants to read location 0x24 A BC D E F G HI • Characteristics Addr[7:0] 0x24 ?? ?? – Asynchronous (no clock) – One Initiator and One Target CMD • Signals Data[7:0] 0x55 ?? ?? – Addr[7:0], Data[7:0], CMD, REQ#, ACK# • CMD=0 is read, CMD=1 is write. REQ# • REQ# low means initiator is requesting something. • ACK# low means target has done its job. ACK# E: Target sets ACK# to low I: Transaction is complete, Bus is idle A: Initiator sets Addr = 0x24, CMD = 0 H: Target sets ACK# to high, Stops driving data G: Initiator sets REQ# high, Stops driving Addr and CMD B: Initiator sets REQ# to low F: Initiator sees data and latches it D: Target drives data C: Target sees read request A B C D E F G H I A read transaction A write transaction • Say initiator wants to read location 0x24 • Say initiator wants to write 0xF4 location 0x31 A. Initiator sets Addr=0x24, CMD=0 A. Initiator sets Addr=0x24, CMD=1, Data=0xF4 B. Initiator then sets REQ# to low B. Initiator then sets REQ# to low C. Target sees read request C. Target sees write request D. Target drives data onto data bus D. Target reads data from data bus (only needs to store in register, not write all the way to E. Target then sets ACK# to low memory) F. Initiator grabs the data from the data bus E. Target then sets ACK# to low. G. Initiator sets REQ# to high, stops driving Addr and F. Initiator sets REQ# to high, stops driving other lines CMD G. Target sets ACK# to high, terminating the transaction H. Target stops driving data, sets ACK# to high H. Bus is seen to be idle. terminating the transaction I. Bus is seen to be idle 2
The push-button Returning to memory-mapped I/O (if Addr=0x04 write 0 or 1 depending on button) Now that we have an example bus, how would memory-mapped I/O work on it? Addr[7] Addr[6] Addr[5] ACK# Addr[4] Example peripherals Addr[3] Addr[2] 0x00000004: Push Button - Read-Only Addr[1] Addr[0] Pushed -> 1 REQ# Data[7] CMD Not Pushed -> 0 Data[6] Data[5] 0x00000005: LED Driver - Write-Only Data[4] On -> 1 Data[3] Data[2] Off -> 0 Data[1] Data[0] Button (0 or 1) 13 The push-button The LED (if Addr=0x04 write 0 or 1 depending on (1 bit reg written by LSB of address button) 0x05) Addr[7] Addr[7] Addr[6] Addr[6] Addr[5] Delay ACK# Addr[5] ACK# Addr[4] Addr[4] Addr[3] Addr[3] Addr[2] Addr[2] Addr[1] Addr[1] Addr[0] Addr[0] Data[7] REQ# REQ# LED CMD CMD Data[6] DATA[7] Data[5] DATA[6] 0 DATA[5] What about Data[4] DATA[4] CMD? DATA[3] Data[3] DATA[2] DATA[1] Data[2] DATA[0] Data[1] Button (0 or 1) Data[0] The LED Let’s write a simple assembly program (1 bit reg written by LSB of address Light on if button is pressed. 0x05) Peripheral Details Addr[7] 0x00000004: Push Button - Read-Only Addr[6] Addr[5] Pushed -> 1 Delay ACK# Addr[4] Not Pushed -> 0 Addr[3] Addr[2] 0x00000005: LED Driver - Write-Only Addr[1] Addr[0] D On -> 1 REQ# LED CMD Off -> 0 clock DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2] DATA[1] DATA[0] 18 3
Today… Driving shared wires • It is commonly the case that some shared wires might have more than one potential device that needs to drive them. Memory-Mapped I/O – For example there might be a shared data bus that is used by the targets and the initiator. We saw this in the simple bus. Example Bus with Memory-Mapped I/O – In that case, we need a way to allow one device to control the wires while the others “stay out of the way” Bus Architectures • Most common solutions are: – using tri-state drivers (so only one device is AMBA APB driving the bus at a time) – using open-collector connections (so if any device drives a 0 there is a 0 on the bus otherwise there is a 1) 19 20 Or just say no to shared wires. Wire count • Another option is to not share wires that could • Say you have a single-master bus with 5 other be driven by more than one device... devices connected and a 32-bit data bus. – This can be really expensive. – If we share the data bus using tri-state connections, each device has “only” 32 -pins. • Each target device would need its own – If each device that could drive data has it’s own bus… data bus. • Each slave would need _____ pins for data • That’s a LOT of wires! • The master would need ______ pins for – Not doable when connecting chips on a PCB as you are data paying for each pin. – Quite doable (though not pretty) inside of a chip. • Again, recall pins==$$$$$$. 21 22 What happens when this “instruction” executes? “*reg += 3” is turned into a ld, add, str sequence • Load instruction – A bus read operation commences – The CPU drives the address “reg” onto the address bus #include <stdio.h> – The CPU indicated a read operation is in process (e.g. R/W#) #include <inttypes.h> – Some “handshaking” occurs #define REG_FOO 0x40000140 – The target drives the contents of “reg” onto the data lines – The contents of “reg” is loaded into a CPU register (e.g. r0) main () { • Add instruction uint32_t *reg = (uint32_t *)(REG_FOO); – An immediate add (e.g. add r0, #3) adds three to this value *reg += 3; • Store instruction – A bus write operation commences printf(“0x%x \ n”, *reg); // Prints out new value – The CPU drives the address “reg” onto the address bus } – The CPU indicated a write operation is in process (e.g. R/W#) – Some “handshaking” occurs – The CPU drives the contents of “r0” onto the data lines – The target stores the data value into address “reg” 23 24 4
Details of the bus “handshaking” depend Why use a standardized bus? on the particular memory/peripherals involved • Downsides – Have to follow the specification • SoC memory/peripherals – Probably has actions that are unnecessary – AMBA AHB/APB • Upside – Generic systems • NAND Flash – Allows modules to be reused on different systems – Open NAND Flash Interface (ONFI) • DDR SDRAM – JEDEC JESD79, JESD79-2F, etc. 25 26 Today… Modern embedded systems have multiple busses Atmel SAM3U Memory-Mapped I/O Example Bus with Memory-Mapped I/O Expanded 373 focus Bus Architectures AMBA APB Historical 373 focus 27 28 Actel SmartFusion system/bus architecture Advanced Microcontroller Bus Architecture (AMBA) - Advanced High-performance Bus (AHB) - Advanced Peripheral Bus (APB) AHB APB • High performance • Low power • Pipelined operation • Latched address/control • Burst transfers • Simple interface • Multiple bus masters • Suitable of many peripherals • Split transactions 29 30 5
APB is a fairly simple bus designed to be easy to Notation work with. • Low-cost • Low-power • Low-complexity • Low-bandwidth • Non-pipelined • Ideal for peripherals 31 32 APB bus signals APB bus signals • PSEL • PCLK – Asserted if the current – Clock bus transaction is targeted to this device • PADDR • PENABLE – Address on bus – High during entire • PWRITE transaction other than the first cycle. – 1=Write, 0=Read • PREADY • PWDATA – Driven by target. Similar to our #ACK. – Data written to the Indicates if the target is ready to do I/O device. transaction. Supplied by the Each target has it’s bus own PREADY master/processor. 33 34 A write transfer with no wait states A write transfer with wait states Setup phase begins Setup phase begins with this rising edge with this rising edge Setup Access Setup Wait Wait Access Phase Phase Phase State State Phase 35 36 6
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