Dynamically-Controlled Power-Gated FPGAs: Overview and Current - - PowerPoint PPT Presentation

Dynamically-Controlled Power-Gated FPGAs: Overview and Current Status

8th Cascadia FPGA Workshop August 13th, 2012

Assem Bsoul and Steve Wilton

{absoul, stevew}@ece.ubc.ca Funded by Altera Corp. & NSERC

System-on-Chip Research Group Department of Electrical and Computer Engineering University of British Columbia Vancouver, B.C., Canada

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Power-Gated FPGAs - Vision

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2 IP core 5

IP C1 (Always-on) µProcessor (Power-gated) IP C5 IP C3 IP C4

Controller

IP C2

CAD Tools Power intent

Power domains

• can be powered down when

idle to reduce static power

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Why do we need a new FPGA?

FPGA leakage power is a major component of total power

– Almost the same amount as dynamic power for 28nm

• Cyclone V: Static 32%, Dynamic 42%, I/O 26%*
• Xilinx 7 Series FPGAs: Static 32%, Dynamic 36%, I/O 32%**

High-end FPGAs are power hungry

– Entering an era where we can’t turn it all on at once! – Large power leads to heat issues reliability, cooling cost

Many applications can benefit from lower power FPGAs

– Many applications have regions with long idle periods – E.g., mobile hand-held devices, medical devices, etc.

*Altera WP-01158-2.0: Meeting the Low Power Imperative at 28nm **Xilinx WP389 (v1.1): Lowering Power at 28nm with Xilinx 7 Series FPGAs

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Challenges

FPGAs need to be flexible to support wide range of apps. No prior information about application structure

– Modules’ (power domains) sizes and locations are not known

Always-on

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Challenges – Continued

How applications are mapped to devices? CAD challenges

Application and power specification Physical synthesis on power-gated chip

Architecture challenges:

– Dynamically-controlled power gating regions – Enable routing control signals – Wakeup (inrush) current

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Power-Gated FPGAs

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

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Power-Gated FPGAs – Applications

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

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Applications

Many suitable applications with long idle periods, e.g.:

– Mobile hand-held devices – Head-mounted display system – Medical robot

Example: Head-mounted display system

– Part of internship at Recon Instruments Inc. – NIOS II processor idle for ≈ 80% of the time

Read sensors and render image Sleep

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Applications – Medical Robot Control

Collaboration with Imperial College London

– Kuen Hung Tsoi (Brittle)

Target: improve safety in minimally-invasive surgery

– Control (manually) snake-shaped robot with haptic guidance – Response time ≈ 1ms

Proximity Query algorithm:

– How close to the cylinder wall? – FPGA design with FP computations

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Power-Gated FPGAs – CAD Tools

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

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Power Specification

UPF and CPF are commonly used in industry Or do we need to create a new standard?

– Specify application behaviour, then – Generate power intent and create power controller

create_power_domain PD_blue -include_scope create_power_domain PD_green -elements { I1 } create_supply_net VDD -domain PD_blue create_supply_net VSS -domain PD_blue … create_power_switch PSW -domain PD_blue

• output_supply_port { VDD_SW VDD_SW } \
• input_supply_port { VDD VDD } -control_port { pon pon } \
• on_state { on VDD pon } \
• off_state {off !pon}

create_power_switch PSW -domain PD_blue

• output_supply_port { VDD_SW VDD_SW } \
• input_supply_port { VDD VDD } -control_port { pon pon } \
• on_state { on VDD pon } \
• off_state {off !pon}

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CAD Flow

Maximize resources that can be powered down at run-time.

Placement and Routing Partitioning Floorplanning Synthesis Application and power intent

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CAD Flow

• Constraint placement of power-gated

modules in the device.

• Minimize overlap between always-on and

power-gated modules.

Always-on Always-on

Controller

Example floorplan Placement and Routing Partitioning Floorplanning Synthesis Application and power intent

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CAD Flow

• Group related blocks together (placement).
• Maximize power-gated routing resources (routing).

Placement and Routing Partitioning Floorplanning Synthesis Application and power intent

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Power-Gated FPGAs – Architecture

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

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Architecture

Divide FPGA device into power-controlled regions

– Support dynamically-controlled sleep mode

Use general-purpose routing fabric for control signals

Power controller

Power domain Power gating region Power control signal Power control signal Designed on FPGA resources

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Power Gating Region

Architecture granularity

• Share sleep transistor among

“region” of tiles.

Control signal from bordering routing channels. Interesting tradeoff:

• Area vs. CAD difficulty

Power gating region, size 2x2

LC SB SB SB SB

CB CB CB CB

LC SB SB

CB CB CB

LC SB SB

CB CB CB

LC SB

CB CB VDD

1 PG_CNTL

From bordering connection blocks

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Power-Gated Switch Blocks

Turn off idle SBs

– Currently we turn off each SB as a unit – Future work: fracturable SB turn off

Always-on SBs are used to:

– route power control signals – route signals between different modules in an app.

SLEEP

Configured to always-on Configured to dynamically-controlled

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Wakeup (Inrush) Current

Inrush current during the wakeup phase

– Amount need to be limited to a safe limit – No prior information about which regions to turn on sequentially OFF

Power-gated Module VDD

SLEEP

Power switch

Current (mA) Time Voltage on power grid

ON

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Handling Inrush Current

PDE size (number of inputs) ≡ the largest power-gated app. that can be turned on using one control signal.

∆T MUX SRAM ∆T ∆T ∆T ∆T ∆T in

• ut

Programmable delay element (PDE)

Power Gating Region

VDD

1

SLEEP From bordering routing channels P D E Virtual VDD

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Handling Inrush Current – Example 1

C1 C1 C1 C1

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Handling Inrush Current – Example 2

C1 C1 C1 C1 C2 C2

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Power Saving Results

Logic clusters and SBs are powered down in a module

– Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size

Region size = 2x2

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Power Saving Results

Logic clusters and SBs are powered down in a module

– Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size

Region size = 2x2 Region size = 3x3

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Power Saving Results

Logic clusters and SBs are powered down in a module

– Assume worst-case always-on SBs = 32% of SBs in a module – Sweep module size

Region size = 2x2 Region size = 3x3 Region size = 4x4 For module size 24x24 tiles, region size = 4x4, savings are 70%

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Current Status

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

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Current Status

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

• Implementing robot control
• next: evaluation

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Current Status

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

• Packing with constraints
• next: high level and low level

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Current Status

Architecture Application

IP core 3 IP core 4 IP core 1 µProcessor IP core 2

Always-on Always-on

Controller

CAD Tools Power intent

• Logic blocks power gating
• Handling inrush current
• next: switch blocks power gating

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Contributors

Steve Wilton (Supervisor, UBC) Architecture

– Assem Bsoul (UBC)

Power Model

– Jeffrey Goeders (UBC) >>>>>>>>>>>>>

CAD

– Alshahna Jamal (UBC)

Application

– Kuen Hung Tsoi (Imperial College London)

Power Specification

– Kenneth Kent (UNB)