Designing Scalable HPC, Deep Learning, Big Data, and Cloud - PowerPoint PPT Presentation

Designing Scalable HPC, Deep Learning, Big Data, and Cloud Middleware for Exascale Systems Talk at SCEC ’18 Workshop by Dhabaleswar K. (DK) Panda The Ohio State University E-mail: panda@cse.ohio-state.edu http://www.cse.ohio-state.edu/~panda

Increasing Usage of HPC, Big Data and Deep Learning Big Data HPC (Hadoop, Spark, (MPI, RDMA, HBase, Lustre, etc.) Memcached, etc.) Convergence of HPC, Big Deep Learning Data, and Deep Learning! (Caffe, TensorFlow, BigDL, etc.) Increasing Need to Run these applications on the Cloud!! Network Based Computing Laboratory SCEC (Dec ‘18) 2

Can We Run Big Data and Deep Learning Jobs on Existing HPC Infrastructure? Physical Compute Network Based Computing Laboratory SCEC (Dec ‘18) 3

Can We Run Big Data and Deep Learning Jobs on Existing HPC Infrastructure? Network Based Computing Laboratory SCEC (Dec ‘18) 4

Can We Run Big Data and Deep Learning Jobs on Existing HPC Infrastructure? Network Based Computing Laboratory SCEC (Dec ‘18) 5

Can We Run Big Data and Deep Learning Jobs on Existing HPC Infrastructure? Hadoop Job Deep Learning Job Spark Job Network Based Computing Laboratory SCEC (Dec ‘18) 6

HPC, Big Data, Deep Learning, and Cloud • Traditional HPC – Message Passing Interface (MPI), including MPI + OpenMP – Exploiting Accelerators • Deep Learning – Caffe, CNTK, TensorFlow, and many more • Big Data/Enterprise/Commercial Computing – Spark and Hadoop (HDFS, HBase, MapReduce) – Deep Learning over Big Data (DLoBD) • Cloud for HPC and BigData – Virtualization with SR-IOV and Containers Network Based Computing Laboratory SCEC (Dec ‘18) 7

Parallel Programming Models Overview P2 P3 P1 P2 P3 P1 P2 P3 P1 Logical shared memory Shared Memory Memory Memory Memory Memory Memory Memory Shared Memory Model Distributed Memory Model Partitioned Global Address Space (PGAS) SHMEM, DSM MPI (Message Passing Interface) Global Arrays, UPC, Chapel, X10, CAF, … • Programming models provide abstract machine models • Models can be mapped on different types of systems – e.g. Distributed Shared Memory (DSM), MPI within a node, etc. • PGAS models and Hybrid MPI+PGAS models are gradually receiving importance Network Based Computing Laboratory SCEC (Dec ‘18) 8

Supporting Programming Models for Multi-Petaflop and Exaflop Systems: Challenges Application Kernels/Applications Co-Design Middleware Opportunities and Programming Models Challenges MPI, PGAS (UPC, Global Arrays, OpenSHMEM), CUDA, OpenMP, across Various OpenACC, Cilk, Hadoop (MapReduce), Spark (RDD, DAG), etc. Layers Communication Library or Runtime for Programming Models Performance Energy- I/O and Fault Point-to-point Collective Synchronization Scalability Communication Communication and Locks Awareness File Systems Tolerance Resilience Networking Technologies Multi-/Many-core Accelerators (InfiniBand, 40/100GigE, Architectures (GPU and FPGA) Aries, and Omni-Path) Network Based Computing Laboratory SCEC (Dec ‘18) 9

Broad Challenges in Designing Runtimes for (MPI+X) at Exascale • Scalability for million to billion processors – Support for highly-efficient inter-node and intra-node communication (both two-sided and one-sided) – Scalable job start-up – Low memory footprint • Scalable Collective communication – Offload – Non-blocking – Topology-aware • Balancing intra-node and inter-node communication for next generation nodes (128-1024 cores) – Multiple end-points per node • Support for efficient multi-threading • Integrated Support for Accelerators (GPGPUs and FPGAs) • Fault-tolerance/resiliency • QoS support for communication and I/O • Support for Hybrid MPI+PGAS programming (MPI + OpenMP, MPI + UPC, MPI + OpenSHMEM, MPI+UPC++, CAF, …) • Virtualization • Energy-Awareness Network Based Computing Laboratory SCEC (Dec ‘18) 10

Overview of the MVAPICH2 Project • High Performance open-source MPI Library for InfiniBand, Omni-Path, Ethernet/iWARP, and RDMA over Converged Ethernet (RoCE) – MVAPICH (MPI-1), MVAPICH2 (MPI-2.2 and MPI-3.1), Started in 2001, First version available in 2002 – MVAPICH2-X (MPI + PGAS), Available since 2011 – Support for GPGPUs (MVAPICH2-GDR) and MIC (MVAPICH2-MIC), Available since 2014 – Support for Virtualization (MVAPICH2-Virt), Available since 2015 – Support for Energy-Awareness (MVAPICH2-EA), Available since 2015 – Support for InfiniBand Network Analysis and Monitoring (OSU INAM) since 2015 – Used by more than 2,950 organizations in 86 countries – More than 511,000 (> 0.5 million) downloads from the OSU site directly – Empowering many TOP500 clusters (Nov ‘18 ranking) 3 rd ranked 10,649,640-core cluster (Sunway TaihuLight) at NSC, Wuxi, China • 14 th , 556,104 cores (Oakforest-PACS) in Japan • 17 th , 367,024 cores (Stampede2) at TACC • 27 th , 241,108-core (Pleiades) at NASA and many others • – Available with software stacks of many vendors and Linux Distros (RedHat, SuSE, and OpenHPC) – http://mvapich.cse.ohio-state.edu Partner in the upcoming TACC Frontera System • Empowering Top500 systems for over a decade Network Based Computing Laboratory SCEC (Dec ‘18) 11

Network Based Computing Laboratory Number of Downloads 100000 200000 300000 400000 500000 600000 0 MVAPICH2 Release Timeline and Downloads Sep-04 Feb-05 Jul-05 Dec-05 MV 0.9.4 May-06 Oct-06 MV2 0.9.0 Mar-07 Aug-07 Jan-08 MV2 0.9.8 Jun-08 Nov-08 Apr-09 MV2 1.0 Sep-09 Feb-10 MV 1.0 Jul-10 SCEC (Dec ‘18) MV2 1.0.3 Dec-10 MV 1.1 May-11 Timeline Oct-11 Mar-12 MV2 1.4 Aug-12 Jan-13 MV2 1.5 Jun-13 Nov-13 MV2 1.6 Apr-14 Sep-14 MV2 1.7 Feb-15 Jul-15 MV2 1.8 Dec-15 May-16 MV2 1.9 Oct-16 MV2-GDR 2.0b Mar-17 MV2-MIC 2.0 MV2 Virt 2.2 Aug-17 Jan-18 MV2 2.3 MV2-X 2.3rc1 Jun-18 OSU INAM 0.9.4 MV2-GDR 2.3 Nov-18 12

Architecture of MVAPICH2 Software Family High Performance Parallel Programming Models PGAS Hybrid --- MPI + X Message Passing Interface (UPC, OpenSHMEM, CAF, UPC++) (MPI + PGAS + OpenMP/Cilk) (MPI) High Performance and Scalable Communication Runtime Diverse APIs and Mechanisms Point-to- Remote Energy- Fault Collectives I/O and Active Introspection point Job Startup Virtualization Memory Algorithms Messages & Analysis Awareness Tolerance File Systems Primitives Access Support for Modern Multi-/Many-core Architectures Support for Modern Networking Technology (InfiniBand, iWARP, RoCE, Omni-Path) (Intel-Xeon, OpenPower, Xeon-Phi, ARM, NVIDIA GPGPU) Modern Features Transport Protocols Transport Mechanisms Modern Features SR- Multi Shared RC UMR ODP MCDRAM * NVLink * CAPI * XRC UD DC CMA IVSHMEM XPMEM Rail Memory IOV * Upcoming Network Based Computing Laboratory SCEC (Dec ‘18) 13

MVAPICH2 Software Family Requirements Library MPI with IB, iWARP, Omni-Path, and RoCE MVAPICH2 Advanced MPI Features/Support, OSU INAM, PGAS and MPI+PGAS MVAPICH2-X with IB, Omni-Path, and RoCE MPI with IB, RoCE & GPU and Support for Deep Learning MVAPICH2-GDR HPC Cloud with MPI & IB MVAPICH2-Virt Energy-aware MPI with IB, iWARP and RoCE MVAPICH2-EA MPI Energy Monitoring Tool OEMT InfiniBand Network Analysis and Monitoring OSU INAM Microbenchmarks for Measuring MPI and PGAS Performance OMB Network Based Computing Laboratory SCEC (Dec ‘18) 14

Overview of A Few Challenges being Addressed by the MVAPICH2 Project for Exascale • Scalability for million to billion processors – Support for highly-efficient inter-node and intra-node communication – Scalable Start-up – Optimized Collectives using SHArP and Multi-Leaders – Optimized CMA-based and XPMEM-based Collectives – Asynchronous Progress • Exploiting Accelerators (NVIDIA GPGPUs) • Optimized MVAPICH2 for OpenPower (with/ NVLink) and ARM • Application Scalability and Best Practices Network Based Computing Laboratory SCEC (Dec ‘18) 15

One-way Latency: MPI over IB with MVAPICH2 Large Message Latency Small Message Latency 120 2 TrueScale-QDR 1.8 ConnectX-3-FDR 100 1.19 1.6 ConnectIB-DualFDR 1.15 1.4 80 ConnectX-5-EDR Latency (us) Latency (us) 1.2 Omni-Path 60 1 1.11 0.8 40 1.04 0.6 0.98 0.4 20 0.2 0 0 Message Size (bytes) Message Size (bytes) TrueScale-QDR - 3.1 GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-3-FDR - 2.8 GHz Deca-core (IvyBridge) Intel PCI Gen3 with IB switch ConnectIB-Dual FDR - 3.1 GHz Deca-core (Haswell) Intel PCI Gen3 with IB switch ConnectX-5-EDR - 3.1 GHz Deca-core (Haswell) Intel PCI Gen3 with IB Switch Omni-Path - 3.1 GHz Deca-core (Haswell) Intel PCI Gen3 with Omni-Path switch Network Based Computing Laboratory SCEC (Dec ‘18) 16