CSE 291E / EE260C Spring 2002 Overview Overview of Tensilica - - PowerPoint PPT Presentation

Configurable Cores: XTensa

CSE 291E / EE260C Spring 2002

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Overview

• Overview of Tensilica
• Overview of XTensa

– Design Flow – Base ISA – Optional Components – TIE

• Challenges for Customized Processors

– What are the problems? – How does XTensa address them? – What could be done better?

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Tensilica: The Company

• Founder/CEO/Mastermind - Chris Rowen

– from Intel, Stanford, MIPS, sgi, Synopsys

• Idea: Build customizable processor design chain
• Strategic Investors

– Cisco, Matsushita, Altera, Conexent, NEC

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Motivation: The “Design Gap”

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Motivation: Before

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Motivation: With XTensa

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Design Flow - high level

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Design Flow – detailed

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Xtensa ISA Priorities

• Code Size

– Large factor in system cost

• Configurability, Extensability

– Provide match to requirements

• Processor Cost

– More than just area?

• Energy Efficiency
• Performance
• Scalability
• Features

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Xtensa ISA

• RISC architecture
• 5-stage Pipeline

– I R E M W

• 24/16 bit instructions

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Xtensa Pipeline

Instruction RAM Instruction Cache Instruction ROM Decode General Registers CoProcessor Registers XLMI Data ROM Data Cache Data RAM Instruction ROM Address Generation ALU CoProcessor ALU

I R E M W

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XTensa Architecture

Processor Controls Align and Decode ALU Instruction Fetch Unit Data Load/Store Unit

Base ISA

Mac16 Mul16 Mul32 FPU Vectra DSP Trace port JTAG Tap Control On-Chip Debug Exception Control

Optional

Data Address Watch 0 -n Instr Address Watch 0 -n Interupt Control Timers 0 -n Instruction ROM Instruction RAM Instruction Cache Data ROM Data RAM Data Cache XLMI

Optional & Configurable

Register File Instr TLB Data TLB

Configurable

Designer defined register files Designer Defined Execution Units

Advanced

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TIE

• Major parts of TIE

– Instruction Fields – Opcodes – Operands – State and Register – Instruction Semantics – Compiler Prototype – Pipelining/Scheduling

• What do we need to worry about?

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TIE Overiew

• No micro-architecture details

– Same TIE will work with new base – Decode, interlock, bypass, and pipelining, OS support of context switch automatic

• Automatic configuration of software tools

– Compiler – Instruction-set simulator – Debugger

• Automatic Synthesis

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TIE E xample: ADD4

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TIE E xample: Accum

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Code Size

• Small Encoding Size

– 24/16 bits – Mode-less encoding

• Code savings from elimination of save/restore

– Special instruction now handles this – Estimate 6-10% Reduction in code size

• Compound Instructions

– Loop instructions / Compare-and-Branch – Shift-Add/Subtract – Shift-Mask

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Instruction E ncoding

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E xample Code

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What are the challenges?

• Layout / Synthesis
• Code Size
• Verification
• Ease/Speed of use

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Layout / Synthesis

• Not Full Custom
• One Clock

– Rising Edge Triggered – No standard processor tricks

• No time borrowing
• Caches

– Generated with memory compiler – Registered address input

• Use hints to layout tools to make sure there is a

sane placement

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Code Size

• Small instruction encoding
• Compound instructions
• Register Windows
• Section/Pooling Literals
• What else could we do?

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Verification

• Directed Diagnostics
• Psuedo-Random program generator
• Coverage Analysis

– Architecture level (AVP) – Micro-architecture level (MVP) – Random generator – Cycle accurate simulator -> Co-simulation

• What else?

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E ase/ Speed of use

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Conclusions and Discussion

• What is next for Tensilica and Customized

processors in the future?

– CMP? – Vector? – FPGA based? – Tile based? – What about further out?