CSCI-2500: Computer Organization
Boolean Logic & Arithmetic for Computers (Chapter 3 and App. B)
CSCI-2500: Computer Organization Boolean Logic & Arithmetic for - - PowerPoint PPT Presentation
CSCI-2500: Computer Organization Boolean Logic & Arithmetic for Computers (Chapter 3 and App. B) Boolean Algebra Developed by George Boole in the 1850s Mathematical theory of logic. Shannon was the first to use Boolean Algebra
Boolean Logic & Arithmetic for Computers (Chapter 3 and App. B)
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Algebra to solve problems in electronic circuit design. (1938)
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written as +, as in
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either of the operands is a 1.
when both operands are 0s.
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both operands are 1s.
multiplication, but operates on binary values.
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NOT is a 0.
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Boolean algebra uses equations to express
This equation expressed a relationship between the value of X and the values
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What is the value of each X:
4 4 3 2 1
huh?
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Just like in good old algebra, Boolean Algebra has postulates and identities. We can often use these laws to reduce expressions or put expressions in to a more desirable form.
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everything else can be derived.
Commutative laws Distributive laws Identity Inverse
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Can be derived from the basic postulates. Laws of Ones and Zeros Associative Laws DeMorgan’s Theorems
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Law of Ones Law of Zeros
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functionally complete set!
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variables.
either a 0 or a 1.
f(a,b) = a+b
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showing it using algebraic operations.
by listing the value of the function for all possible inputs.
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a b for(a,b) 1 1 1 1 1 1 1
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a b OR AND NOR NAN D XOR 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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X Y Z (X+Y)·Z 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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that are implementations of some Boolean function(s).
implements some simple logic function.
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Inputs Output A B f(A,B)
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change.
does not change.
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any Boolean function!
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A B
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a b a b a • b a • b 1 1 1 1 1 1 1 1 1 1 1 1
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Boolean Equation Circuit (Logic Diagram) Truth Table
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implementation of a function.
and the way they are connected.
together (along with a power source) and build a machine.
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truth table or Boolean Equation, there are many possible implementations.
what kind of gates are available.
number of gates.
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A B f
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A B f
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B A A B B A A B B A A B B B B A A B A A B B A A B A B A B A B A B A B A B A +
=
+
= +
=
DeMorgan's Laws Distributive Distributive Inverse, Identity DeMorgan's Law DeMorgan's Laws
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components in processor design.
design control systems (later).
design of some of these components now.
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is turned on.
1 output.
become the output.
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Decoder
I0 I1 O0 O2 O1 O3
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I0 I1 O0 O1 O2 O3 1 1 1 1 1 1 1 1
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1 3 1 2 1 1 1
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I0 I1 O0 O1 O2 O3
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Decoder
I0 I1 O0 O2 O1 O3 O4 O6 O5 O7 I3
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I2 I1 I0 O0 O1 O2 O3 O4 O5 O6 O7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 2 1
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I0 I1 O0 I2 O1
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The above logic diagram is often abbreviated as shown below: We can do this (without possible confusion) because of the associative property.
C A B A • B • C C A B A • B • C
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I0 I1 O0 I2 O1
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C A B C A B A+B+C A+B+C A B C A B A+B+C+D A+B+C+D C D D
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Inputs: I0 and I1 Selector: S Output: O If S is a 0: O=I0 If S is a 1: O=I1 Mux
I0 I1 O S
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1
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S O 0 I0 1 I1
Abbreviated Truth Table S I0 I1 O0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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1
Since S can’t be both a 1 and a 0, only
terms
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I1 I0 S O
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selection bits: S0 S1 S0 S1 O I0 1 I1 1 I2 1 1 I3
Abbreviated Truth Table
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2-Decoder
I0 I1 I2 I3 S0 S1 O
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used in many circuit implementations:
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combinations of inputs for which the output should be a 1.
table where the function has the value 1.
gate.
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Find rows in truth table where the output is 1. If S is 1 in that row, connect S to a 3-input AND gate,
Connect I0 and I1 in the same way. The AND gate corresponds to the row in the truth table. S I0 I1 O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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S I0 I1 O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
S I0 I1 If the output of this AND gate is a 1,the value of the function is a 1!
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the value 1 (the function has the value 1) build the corresponding AND gate.
the value 0!
to one big OR gate.
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O
S I0 I1 O0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I0 I0 S I1 I0 S I1 I0 I1 S I1 S
Truth Table
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combinations of inputs for which the output should be a 0.
table where the function has the value 0.
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Find rows in truth table where the output is 0. If S is 0 in that row, connect S to a 3-input OR gate,
Connect I0 and I1 in the same way. The OR gate corresponds to the row in the truth table. S I0 I1 O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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S I0 I1 O 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
S I0 I1 If the output of this OR gate is a 0, the value of the function is a 0!
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the value 0 (the function has the value 0) build the corresponding OR gate.
the value 1!
to one big AND gate.
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O
I0 I0 S I1 I0 S I1 I1
Truth Table
I0 I1 S S
S I0 I1 O
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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translation from truth table to circuit.
gates than are necessary.
to minimize such circuits.
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expressions.
more than 4 or 5 inputs)
computer program.
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matter what the value of A is!
function:
C B A C B A f
C B f
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will be easy to see when terms can be merged.
result is similar to a Venn Diagram
A B C
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A B f
1 1 1 1 1 1
B=0 B=1 A=0
1
A=1
1
Truth Table K-Map In the K-Map it’s easy to see that the value of A doesn’t matter
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the majority of the inputs are 1.
the 3-input majority function:
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A B C f
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Truth Table K-Map AB C
00 01 11 10 1 1 1 1 1
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adjacent cells differ by exactly one bit in the input.
B is different or C is different.
variable is different!
AB C
00 01 11 10 1 1 1 1 1
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K-Map AB C
00 01 11 10 1 1 1 1 1
Rectangular collections of cells that all have the value 1 indicate it is possible to merge the corresponding terms in SOP expression. The number of cells in the rectangle must be a power of 2!
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mergings of terms in this K-Map.
K-Map AB C
00 01 11 10 1 1 1 1 1
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means “if C is 1 and B is 1, it doesn’t matter what the value of A is”
K-Map AB C
00 01 11 10 1 1 1 1 1
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K-Map AB C
00 01 11 10 1 1 1 1 1
C B A C B A C B A C B A f
Original: Reduced:
B A C A C B f
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need to use minimization techniques every day.
know is the general idea.
minimizing SOP and POS form Boolean equations.
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completely on the value of the inputs.
state a little while ago.
time in the past.
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combinational circuit that could be used as a single bit memory.
the inputs change.
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A B C A B C Δt Δt
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0?
A C
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S R Q Q A B A nor B
1 1 1 1 1
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S R Q Q Qt St Rt Qt+1 1 1 1 1 1 0? 1 1 1 1 1 1 1 1 1 1 0?
If S and R = 1, then Q’s
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S R Q Q Q Q S R
1 1 1 1
Δt Δt 2Δt 2Δt
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times.
that changes occur only when a clock changes (when the clock changes from 0 to 1).
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S R Q Q Clock
gates.
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we have a clock.
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D Q Q Clock
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D Q Q Clock
circuit will remember the value 1 (Q=1).
circuit will remember the value 0 (Q=0).
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Q D Clock
1 1 1
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bit memory.
all are written at the same time.
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D Flip-Flop
D clock Q
D Flip-Flop D Flip-Flop D Flip-Flop D Flip-Flop D Flip-Flop D Flip-Flop D Flip-Flop D Flip-Flop
D0 D1 D3 D4 D5 D6 D2 D7 clock Q0 Q1 Q3 Q4 Q5 Q6 Q2 Q7
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digit
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0.0V 0.5V 2.8V 3.3V 1
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types
“process”
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111111112
010 to 25510
to FF16
0000 1 1 0001 2 2 0010 3 3 0011 4 4 0100 5 5 0101 6 6 0110 7 7 0111 8 8 1000 9 9 1001 A 10 1010 B 11 1011 C 12 1100 D 13 1101 E 14 1110 F 15 1111
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applications
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Word-Oriented Memory Organization
Byte Locations
byte in word
successive words differ by 4 (32-bit)
0000 0001 0002 0003 0004 0005 0006 0007 0008 0009 0010 0011 32-bit Words Bytes Addr. 0012 0013 0014 0015 64-bit Words
Addr = ?? Addr = ?? Addr = ?? Addr = ?? Addr = ?? Addr = ?? 0000 0004 0008 0012 0000 0008
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Intel IA32
4 4 4
8 4 4
1 1 1
2 2 2
4 4 4
8 8 8
8 8 10/12
8 4 4
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be ordered in memory?
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0x100 0x101 0x102 0x103
01 23 45 67
0x100 0x101 0x102 0x103
67 45 23 01 Big Endian Little Endian 01 23 45 67 67 45 23 01
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Address Instruction Code Assembly Rendition 8048365: 5b pop %ebx 8048366: 81 c3 ab 12 00 00 add $0x12ab,%ebx 804836c: 83 bb 28 00 00 00 00 cmpl $0x0,0x28(%ebx)
0x12ab
0x000012ab
00 00 12 ab
ab 12 00 00
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array
typedef unsigned char *pointer; void show_bytes(pointer start, int len) { int i; for (i = 0; i < len; i++) printf("0x%p\t0x%.2x\n", start+i, start[i]); printf("\n"); } Printf directives: %p: Print pointer %x: Print Hexadecimal
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int a = 15213; printf("int a = 15213;\n"); show_bytes((pointer) &a, sizeof(int));
Result (Linux):
int a = 15213; 0x11ffffcb8 0x6d 0x11ffffcb9 0x3b 0x11ffffcba 0x00 0x11ffffcbb 0x00
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Decimal: 15213 Binary: 0011 1011 0110 1101 Hex: 3 B 6 D 6D 3B 00 00 Linux/Alpha A 3B 6D 00 00 Sun A 93 C4 FF FF Linux/Alpha B C4 93 FF FF Sun B Two’s complement representation (Covered in future) 00 00 00 00 6D 3B 00 00 Alpha C 3B 6D 00 00 Sun C 6D 3B 00 00 Linux C
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Alpha Address Hex: 1 F F F F F C A 0 Binary: 0001 1111 1111 1111 1111 1111 1100 1010 0000 01 00 00 00 A0 FC FF FF Alpha P Sun Address Hex: E F F F F B 2 C Binary: 1110 1111 1111 1111 1111 1011 0010 1100 Different compilers & machines assign different locations to objects FB 2C EF FF Sun P FF BF D4 F8 Linux P Linux Address Hex: B F F F F 8 D 4 Binary: 1011 1111 1111 1111 1111 1000 1101 0100
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IEEE Single Precision Floating Point Representation Hex: 4 6 6 D B 4 0 0 Binary: 0100 0110 0110 1101 1011 0100 0000 0000 15213: 1110 1101 1011 01 Not same as integer representation, but consistent across machines 00 B4 6D 46 Linux/Alpha F B4 00 46 6D Sun F Can see some relation to integer representation, but not obvious IEEE Single Precision Floating Point Representation Hex: 4 6 6 D B 4 0 0 Binary: 0100 0110 0110 1101 1011 0100 0000 0000 15213: 1110 1101 1011 01 IEEE Single Precision Floating Point Representation Hex: 4 6 6 D B 4 0 0 Binary: 0100 0110 0110 1101 1011 0100 0000 0000 15213: 1110 1101 1011 01
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n char S[6] =
"15213";
character(s)!
Linux/Alpha S Sun S 32 31 31 35 33 00 32 31 31 35 33 00
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machines
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int y)
Different machines use totally different instructions and encodings 00 00 30 42 Alpha sum 01 80 FA 6B E0 08 81 C3 Sun sum 90 02 00 09
n For this example, Alpha & Sun
use two 4-byte instructions
n Use differing numbers of
instructions in other cases
n PC uses 7 instructions with
lengths 1, 2, and 3 bytes
n Same for NT and for Linux n NT / Linux not fully binary
compatible
E5 8B 55 89 PC sum 45 0C 03 45 08 89 EC 5D C3
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~010000012 --> 101111102
~000000002 --> 111111112
011010012 & 010101012 --> 010000012
011010012 | 010101012 --> 011111012
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(avoids null pointer access)
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x << y
x >> y
right
integer representation 01100010 Argument x 00010000 << 3 00011000
00011000
10100010 Argument x 00010000 << 3 00101000
11101000
00010000 00010000 00011000 00011000 00011000 00011000 00010000 00101000 11101000 00010000 00101000 11101000
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void swap(int *x, int *y) { *x = *x ^ *y; /* #1 */ *y = *x ^ *y; /* #2 */ *x = *x ^ *y; /* #3 */ }
property that every value is its own additive inverse A ^ A = 0
B A Begin B A^B 1 (A^B)^B = A A^B 2 A (A^B)^A = B 3 A B End *y *x
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range (would require infinite storage).
broad categories of integer representation have been developed: unsigned integers and signed integers.
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computer can store depends on the number of bits the computer allocates to store an unsigned integer.
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1 1 1 1 carry 0 0 0 1 0 0 1 1 19 0 0 0 1 0 1 1 1 23 0 0 1 0 1 0 1 0 42
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250 and 8
will be 2, which is (250 + 8) modulo 256
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number that is not within the range defined by the allocation.
stored is 255; however, the result of the addition is 258.
when there are insufficient bits to represent a number in binary.
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numbers.
computer; therefore, we have to devise a scheme for representing negative numbers.
two's complement.
representation.
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sign.
make a total of 8 bits
needed.
bit (i.e. change from 0 to 1 or from 1 to 0)
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0 0 0 1 1 0 0 1 25 = (2^4 + 2^3 + 2^0)
each bit 1 1 1 0 0 1 1 0 -25
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+0 00000000
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from binary to decimal.
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representation to decimal:
number: 00001110
number, just do the direct binary to decimal conversion.
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representation for negative numbers.
For -13: 00001101 base integer 11110010 1's complement +1 11110011 2's complement
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add two bits and propagate the carry to the next column. If there is a final carry after the leftmost column addition, discard it. Add -25 and 20: 1 1 1 0 0 1 1 1 (-25) 0 0 0 1 0 1 0 0 ( 20) 1 1 1 1 1 0 1 1
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complement, the sum of a number and its two's complement is always 0
twos_complement(b) (i.e., flip bits and add 1)
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+12 = 000011002
0 000000002
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decimal.
number
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arithmetic operations and logic
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larger ALUs.
simple for some operations, can be tricky for others.
them together to build larger units.
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can compute either AND or OR.
determine which operation is performed.
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Op A B Result 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A B Op Result Op=0: Result is A•B Op=1: Result is A+B
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the corresponding logic.
be used.
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Mux
Result A B Op
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bits.
A B O0 O1 1 1 1 1 1 1 1 A + B O0 O1 This is addition, not logical OR!
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A B O0 A B A B O1
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What we really want is something that can be used to implement the binary addition algorithm.
01001 + 01101 10110
1 1 Carry
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01001 + 01101 10110
1 1 Carry
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A B Carry In Carry Out Sum 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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the truth table.
that implements the SOP expressions.
name.
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adder
A B Carry In Carry Out Sum
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2 selection inputs. AND OR add
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b 2 Result Operation a 1 CarryIn CarryOut
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A0 A1 … A31 B0 B1 … B31 … … Op R0 R1 … R31 …
Result
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Result31 a31 b31 Result0 CarryIn a0 b0 Result1 a1 b1 Result2 a2 b2 Operation ALU0 CarryIn CarryOut ALU1 CarryIn CarryOut ALU2 CarryIn CarryOut ALU31 CarryIn
Ripple Carry Adder
sent to carry in of ALU1
the result to become available?
propagate through all 32 1-Bit ALUs.
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A - B can be computed as A + -B
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1!
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2 Result Operation a 1 CarryIn CarryOut 1 Binvert b
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instructions can be implemented with
ALU and set control lines.
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slt needs to compare 2 numbers.
if A-B is negative, then A<B is true.
True: output should be 0000000…001 False: output should be 0000000…000
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the L.S. Carry In to 1.
should always be 0.
the result bit from the MS 1-bit ALU!
LS: Least significant (rightmost) MS: Most significant (leftmost)
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3 R e s u lt O p e r a ti o n a 1 C a rr y I n C a r r y O u t 1 B i n v e rt b 2 L e s s
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3 R e s u l t O p e r a t i o n a 1 C a r r y I n 1 B i n v e r t b 2 L e s s S e t O v e r f l o w d e t e c t i o n O v e r f l o w .
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Set a31 ALU0 Result0 CarryIn a0 Result1 a1 Result2 a2 Operation b31 b0 b1 b2 Result31 Overflow Binvert CarryIn Less CarryIn CarryOut ALU1 Less CarryIn CarryOut ALU2 Less CarryIn CarryOut ALU31 Less CarryIn
all but the LS.
the MS ALU is fed back to the Less input of the LS ALU
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ALU Result Zero Overflow a b ALU operation CarryOut
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takes to do an addition is too long.
from the i-1th ALU.
delays before the addition is complete.
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each of the 32 result bits as a function
for each and implement using 2 levels of gates.
couldn’t carry the tests to class…
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compute.
as fast as possible
carry-in bits much faster (but not in constant time).
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the ith 1 bit adder.
connected to CarryIni
compute the CarryOuts
A B Cary In Cary Out Sum 0 0 0 0 1 0 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1
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CarryIn1 = (B0• CarryIn0) + (A0 • CarryIn0)+(A0 • B0)
SOP: Requires 2 levels of gates
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CarryIn2 = (B1• CarryIn1) + (A1 • CarryIn1)+(A1 • B1) We can substitute for CarryIn1 and get this mess: CarryIn2 = (B1• B0• CarryIn0) + (B1• A0 • CarryIn0)+(B1• A0 • B0) + (A1 • B0• CarryIn0) + (A1
The size of these expressions will get too big (that’s the whole problem!).
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Ci+1 = (Bi• Ci) + (Ai • Ci)+(Ai • Bi) = (Ai • Bi) + (Ai + Bi) •Ci Ai • Bi : Call this Generate (Gi) Ai + Bi : Call this Propagate (Pi) Ci+1 = Gi + Pi • Ci
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Out. Ci+1 = Gi + Pi • Ci Gi =Ai • Bi Pi =Ai + Bi
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C1 = G0+P0•C0 C2 = G1+P1•C1 = G1+ P1• (G0+P0•C0) = G1+ P1• G0 + P1• P0•C0 C3 = G2 + P2•G1 + P2•P1•G0 + P2•P1•P0•C0
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(for 32 bits).
compute all the CarryIn bits for a 4 bit adder.
together and treat CarryIns to these adders in the same manner.
CSCI-2500 SPRING 2016, Boolean Logic
CarryIn Result0--3 ALU0 CarryIn Result4--7 ALU1 CarryIn Result8--11 ALU2 CarryIn CarryOut Result12--15 ALU3 CarryIn C1 C2 C3 C4 P0 G0 P1 G1 P2 G2 P3 G3 pi gi pi + 1 gi + 1 ci + 1 ci + 2 ci + 3 ci + 4 pi + 2 gi + 2 pi + 3 gi + 3 a0 b0 a1 b1 a2 b2 a3 b3 a4 b4 a5 b5 a6 b6 a7 b7 a8 b8 a9 b9 a10 b10 a11 b11 a12 b12 a13 b13 a14 b14 a15 b15 Carry-lookahead unit