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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Abdelkrim Kamel Oudjida C entre de D veloppement des T echnologies A vances Algiers, Algeria CDTA Septembre 10 th 2010, Grenoble, France Controlled-Precision Pure-Digital

SLIDE 1

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Abdelkrim Kamel Oudjida Centre de Développement des Technologies Avancées Algiers, Algeria Septembre 10th 2010, Grenoble, France

CDTA

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Problem

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

( )

1 U B R 1 6 f B A U D

C K

+ =

ATMEL Baud-Rate UBR Settings at Various Cristal Frequencies Source: ATMEL

( ) ( ) ( )

100 desired Baud actual Baud desired Baud Error % × − =

< 1% Error Equation ( )

1 ︶︵ S P R C K

2 1 S P P R f B A U D

⋅ + =

MOTOROLA Baud-Rate ( )

D i v A d d V a l M u l V a l M u l V a l U D L L U D L M 1 6 1 6 f B A U D

C K

+ ⋅ + ⋅ ⋅ =

PHILIPS Baud-Rate

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Objective

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Controlled-Precision Frequency Synthesizer

X Y in

F

F Y X F ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ =

in c

F K F ⋅ =

;

( )

⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = X Y . K K g

;

( )

in in c

F Y X X Y K F K F F ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ⋅ = = K g

Simplified Version of an Existing Algorithm Block Diagram of the Frequency Synthesizer

r Y K Y K + ⋅ ⋅ Y r < ≤

where

Source of Error

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Solution

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Double Simpling Technique on N Cycles of Fin 50% Duty Cycle Technique

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Features

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Precision

( )

1 X Y 1 K N 2 1 1 1 − ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + ⋅ ⋅ −

Error = Jitter = Duty-Cylce = (40% - 60%)

Switching Time

Latency = N.Tin + 2Tc

Frequency Bandwidth

Fin & Fout ≤ Fc_Max Size = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ X N Y Floor 2 Tc

( )⎥

⎦ ⎤ ⎢ ⎣ ⎡ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + N / 1 K 2 1 . Y X 2 1

⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅ − ⋅ ≥ N 2 1 Y X 5 Ceil K

( )

( ) [ ]

size _ bit _ reg _ Y 2

2 2 K N 2 Log Ceil ⋅ + ⋅ ⋅

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Features

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Main Features of the Solution

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Physical Test

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Main Features of the Solution Error Comparison

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Characterisation

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Frequency Bandwidth (Fc_Max) for N=1, X & Y Register Size = 8 Bits

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Characterisation

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Slice Utilization for N=1, X & Y Register size = 8 Bits

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Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Applications

A.K. Oudjida, PATMOS’10, September 10th 2010, Grenoble, France. Email: a_oudjida@cdta.dz

CDTA

Error (%) Versus N Parameter

Baud Rate Generator

5 389 2 = = ⇒ = = ⇒ =

in c c

F F K MHz F Y X MHz Y X 9 . 2 1 6 1 . 8 4 3 2 9 6

Pulse Width Modulation

( Fout ; D ) such that

T T = D

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Abdelkrim Kamel Oudjida Centre de Développement des Technologies Avancées Algiers, Algeria Septembre 10th 2010, Grenoble, France

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Problem

( ) ( ) ( )

100 desired Baud actual Baud desired Baud Error % × − =

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Objective

F

F Y X F ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ =

F K F ⋅ =

;

( )

⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = X Y . K K g

;

( )

F Y X X Y K F K F F ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = ⋅ = = K g

r Y K Y K + ⋅ ⋅ Y r < ≤

where

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Solution

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Features

Precision

( )

1 X Y 1 K N 2 1 1 1 − ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ + ⋅ ⋅ −

Error = Jitter = Duty-Cylce = (40% - 60%)

Switching Time

Latency = N.Tin + 2Tc

Frequency Bandwidth

Fin & Fout ≤ Fc_Max Size = ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ ⋅ ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ X N Y Floor 2 Tc

( )⎥

⎦ ⎤ ⎢ ⎣ ⎡ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + N / 1 K 2 1 . Y X 2 1

⎥ ⎦ ⎤ ⎢ ⎣ ⎡ ⋅ − ⋅ ≥ N 2 1 Y X 5 Ceil K

( )

( ) [ ]

2 2 K N 2 Log Ceil ⋅ + ⋅ ⋅

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Features

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Physical Test

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Characterisation

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Characterisation

Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer

Applications

Baud Rate Generator

5 389 2 = = ⇒ = = ⇒ =

F F K MHz F Y X MHz Y X 9 . 2 1 6 1 . 8 4 3 2 9 6

Pulse Width Modulation

( Fout ; D ) such that

Duty-Cylce =

( )⎥

⎦ ⎤ ⎢ ⎣ ⎡ + ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ + N / 1 K 2 1 . Y X D