Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Abdelkrim Kamel Oudjida C entre de D éveloppement des T echnologies A vancées Algiers, Algeria CDTA Septembre 10 th 2010, Grenoble, France
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Problem M = V u a f C K = U D f = ⋅ B A C K ︵ ︶ f l l ( ) U D C K B A U D ( ) B A ( ) + + ⋅ + ⋅ ⋅ + + U B R S P R 1 M M 1 6 1 S P P R U D U D D V A V 1 2 1 6 1 6 0 L 0 L L u a d d a v l l i l PHILIPS Baud-Rate ATMEL Baud-Rate MOTOROLA Baud-Rate Source: ATMEL UBR Settings at Various Cristal Frequencies ( ) ( ) − Baud desired Baud actual = × % Error 100 ( ) Baud desired < 1% Error Equation A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 1/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Objective ⎛ ⎞ X X = ⋅ ⎜ ⎟ F F F out in in ⎝ ⎠ Y Y Controlled-Precision Frequency Synthesizer ⋅ ⎛ ⎞ ⎛ ⎞ F K F X ( ) Y = = = ⎜ ⎟ = ⋅ = c in ⎜ ⎟ F F ; ( ) K K . F K F ; g out in ⎝ ⎠ Y c in ⎝ ⎠ Y K g X K X Simplified Version of an Existing Algorithm ⋅ K Y ⋅ + ≤ < 0 r Y K Y r where Source of Error Block Diagram of the Frequency Synthesizer A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 2/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Solution 50% Duty Cycle Technique Double Simpling Technique on N Cycles of F in A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 3/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Features Precision ⎛ ⎞ ⎛ ⎞ 1 T c Y − ⋅ ⎜ ⎟ ⎜ ⎟ 1 Floor Error = Jitter = ⋅ ⎡ ⎤ ⎝ ⎠ ⎝ ⎠ ( ) Y 2 N X − ⋅ ⋅ + 1 1 2 N K 1 ⎢ ⎥ ⎣ ⎦ X ⎡ ⎤ ⎡ ⎤ ⎛ ⎞ X 1 1 X 1 ≥ ⋅ − + ⎜ ⎟ K Ceil 5 ⎢ ⎥ . ⎢ ) ⎥ Duty-Cylce = (40% - 60%) ( ⋅ + ⎣ ⎦ ⎝ ⎠ ⎣ ⎦ Y 2 N 2 Y 2 K 1 / N Switching Time Latency = N.Tin + 2Tc Frequency Bandwidth [ ] ( ) ( ) F in & F out ≤ F c_Max ⋅ ⋅ + ⋅ Y _ reg _ bit _ size Ceil Log 2 N K 2 2 Size = 2 A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 4/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Features Main Features of the Solution A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 5/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Physical Test Main Features of the Solution Error Comparison A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 6/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Characterisation Frequency Bandwidth (Fc_Max) for N=1, X & Y Register Size = 8 Bits A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 7/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Characterisation Slice Utilization for N=1, X & Y Register size = 8 Bits A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 8/9 CDTA
Controlled-Precision Pure-Digital Square-Wave Frequency Synthesizer Applications Baud Rate Generator 2 X X = ⇒ = MHz 9 6 0 0 1 8 4 3 2 . Y Y 389 F = ⇒ = = c 5 F MHz K 9 2 1 6 . c F in Error (%) Versus N Parameter Pulse Width Modulation T = H D ( F out ; D ) such that T out ⎡ ⎤ ⎛ ⎞ X 1 + ⎜ ⎟ ⎢ ) ⎥ Duty-Cylce = D . ( + ⎝ ⎠ ⎣ ⎦ Y 2 K 1 / N A.K. Oudjida, PATMOS’10, September 10 th 2010, Grenoble, France. Email: a_oudjida@cdta.dz Slide: 9/9 CDTA
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