Comparison'of'Bulk'Built7In' Current'Sensors'(BBICS)'in'terms'of' - - PowerPoint PPT Presentation

1"

October 1st, 2014 – Palma de Mallorca, Spain.

Rodrigo'Possamai'Bastos*;'J.%M."Dutertre;"and"F."Sill"Torres;"

Comparison'of'Bulk'Built7In' Current'Sensors'(BBICS)'in'terms'of' Transient7Fault'DetecAon'SensiAvity'

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'!'Context:'transient'fault'(TF)'effects" """OpAmized'miAgaAon'soluAons" "#"OperaAon'mode'of'a'BBICS' "❹"What'is'TF'detecAon'sensiAvity?' '❺'Comparison'of'BBICS'architectures' '❻'Conclusions'

Outline'

3"

Microscope'image'of'a'nanocircuit'(IBM,'2010)'

Physical'limits' Process'variability' Low'voltage'levels' System'complexity' High'frequencies'

90 nm  65 nm  28 nm 

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" " "Reliability "" " " "Fault"Tolerance" " " " "Security" " ""

Transient'fault'effects'on'ICs'

5"

Environmental Perturbations

Even'at'ground'level'!'

Transient'Faults'

Artificial Sources Natural Sources



6"

Transient'Faults'

Intentional Perturbations

! ! '

!!'

Laser

Good Encryption Results Faulty Encryption Results

Outputs

Input Word

Inputs

Secret Key

Versus

D F A '

7"

Data Register 1 Logic Block 1 Logic Block 2 Data Register 0

Indirect' So\'Error' (e.g.'SEU)'

Clock

Logic Block 0

Clock

Transient'Fault'(e.g.'SET)'

Integrated System

8"

Data Register 1 Logic Block 1 Logic Block 2 Data Register 0

Clock

Logic Block 0

Clock

Integrated System

Direct' So\'Error' (e.g.'SEU)' Transient'Fault'(e.g.'SET)'

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'''1⃣''Nano7systems'

"More"sensiCve"to"transient"faults"

"""2⃣'"Origin'

"Environmental"or"intenConal"sources"

"''3⃣""Logical'effects'

"Indirect"or"direct"soI"errors"

Transient'Faults' !'

Checklist' 1⃣''"""2⃣"""''3⃣""'

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"!" """OpAmized'miAgaAon'soluAons" "#" "❹' '❺' '❻'

Contents'

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'''1⃣''Strategy'

"For"miCgaCon"of"transient"faults"

"""2⃣'"TradiAonal'

"DetecCon"techniques"

"''3⃣""BICS'

"Built%In"Current"Sensors"

MiAgaAon'soluAons' "'

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Logic Block

Clock

Register

Integrated System’s Block

Strategy'

MiAgaAon'soluAons' "'

1⃣''"""2⃣"""''3⃣""'

13"

Concurrent Error Detection Circuitry fault_flag_signal Logic Block

Clock

Register

Integrated System’s Block

MiAgaAon'soluAons' "'

Strategy' 1⃣''"""2⃣"""''3⃣""'

14"

Concurrent Error Detection Circuitry System’s Restart fault_flag_signal System’s Deadlock System’s Recovery

Alternatives of Actions after Detection

• r
• r

Logic Block

Clock

Register

Integrated System’s Block

MiAgaAon'soluAons' "'

Strategy' 1⃣''"""2⃣"""''3⃣""'

15"

MiAgaAon'soluAons' "'

TradiAonal' 1⃣''"""2⃣"""''3⃣""'

Duplication with Comparison (DWC)

Logic Block Data Register

Clock

16"

MiAgaAon'soluAons' "'

TradiAonal' 1⃣''"""2⃣"""''3⃣""'

Duplication with Comparison (DWC)

Logic Block Redundant Register Copy of Logic Block Data Register N Comparator 1

Clock Clock Result

17"

MiAgaAon'soluAons' "'

TradiAonal' 1⃣''"""2⃣"""''3⃣""'

Duplication with Comparison (DWC) Time Redundancy (TR)

Logic Block Redundant Register Copy of Logic Block Data Register N Comparator 1

Clock Clock Result

☹ Area overhead > 2x

Clock

Data Register Logic Block

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☹ Area overhead > 2x ☹ High delay degradation

Clock

Redundant Register Data Register

Clock

N Comparator 1 Delay Logic Block

Result

Logic Block Redundant Register Copy of Logic Block Data Register N Comparator 1

Clock Clock Result

MiAgaAon'soluAons' "'

TradiAonal' 1⃣''"""2⃣"""''3⃣""'

Duplication with Comparison (DWC) Time Redundancy (TR)

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Duplication with Comparison (DWC) Time Redundancy (TR)

Clock

Redundant Register Data Register

Clock

N Comparator 1 Delay Logic Block

Result

Logic Block Redundant Register Copy of Logic Block Data Register N Comparator 1

Clock Clock Result

Built-In Current Sensor (BICS)

$ More efficient than TR $ Much smaller than DWC

Logic Block

Clock

Data Register Fault Register 1 1 BICS

Result

MiAgaAon'soluAons' "'

TradiAonal' 1⃣''"""2⃣"""''3⃣""'

20"

VBICS

PMOS-VBICS NMOS-VBICS

FlagN FlagP

BICS at VDD and VSS

'

MiAgaAon'soluAons' "'

BICS' 1⃣''"""2⃣"""''3⃣""'

21"

VBICS

' 1' ON ' OFF '

PMOS-VBICS NMOS-VBICS

FlagN = 0 FlagP = 0

BICS at VDD and VSS

'

MiAgaAon'soluAons' "'

BICS' 1⃣''"""2⃣"""''3⃣""'

22"

VBICS

' 1 " 0' ON ' OFF ' Ifault

PMOS-VBICS NMOS-VBICS

FlagN = 1 FlagP = 0

BICS at VDD and VSS

'

Alarm Flag

MiAgaAon'soluAons' "'

BICS' 1⃣''"""2⃣"""''3⃣""'

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$ No delay degradation ☹ Delay degradation

☹ Detection of legal transitions $ Detection of only illegal transitions

VBICS

PMOS-VBICS NMOS-VBICS

FlagN FlagP

BICS at VDD and VSS

'

?

MiAgaAon'soluAons' "'

BICS' 1⃣''"""2⃣"""''3⃣""'

24"

BBICS

BICS at Bulk (body-ties) '

PMOS-BBICS NMOS-BBICS

FlagN FlagP

$ No delay degradation ☹ Delay degradation

☹ Detection of legal transitions $ Detection of only illegal transitions

VBICS

PMOS-VBICS NMOS-VBICS

FlagN FlagP

BICS at VDD and VSS

'

MiAgaAon'soluAons' "'

BICS' 1⃣''"""2⃣"""''3⃣""'

25"

'''1⃣''Strategy'

"Error"detecCon"+"CorrecCon"AcCon"

"""2⃣'"TradiAonal'

"DuplicaCon"(+Area);"Time"Redundancy"(+Speed)"

"''3⃣""BICS'

"VBICS"(%Efficiency);"BBICS"(=Speed,"+Efficiency)"

MiAgaAon'soluAons' "'

Checklist' 1⃣''"""2⃣"""''3⃣""'

26"

'!" """ "#"OperaAon'mode'of'a'BBICS' "❹' '❺' '❻'

Contents'

27"

BBICS'OperaAon' #'

'''1⃣''Register'

"IndicaCon"of"fault"

"""2⃣'"ConnecAons'

"BBICS"to"monitored"gates"

"''3⃣""AmplificaAon'

"Anomalous"transient"current"

28"

BBICS'OperaAon' #'

Register' 1⃣''"""2⃣"""''3⃣""'

Reset ' LATCH ' Flag '

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BBICS'OperaAon' #'

ConnecAons' 1⃣''"""2⃣"""''3⃣""'

Monitored Pull-Up Network

Flag ' Reset ' BulkP ' LATCH '

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BBICS'OperaAon' #'

ConnecAons' 1⃣''"""2⃣"""''3⃣""'

Monitored Pull-Down Network Monitored Pull-Up Network

Flag ' Reset ' BulkN ' BulkP ' LATCH '

31"

Vth

BBICS'OperaAon' #'

AmplificaAon' 1⃣''"""2⃣"""''3⃣""'

Monitored Pull-Down Network Monitored Pull-Up Network

Flag ' Reset ' BulkN ' BulkP ' LATCH ' Xn·Wmin " Xp·Wmin "

Vth

32"

BBICS'OperaAon' #'

'''1⃣''Register'

"Asynchronous"latch"to"memorize"fault"flag"

"""2⃣'"ConnecAons'

"High%ohmic"and"pull%up"(and"%down)"transistors"

"''3⃣""AmplificaAon'

"Transistor"sizing:"lower"Vth,"higher"detecCon"

Checklist' 1⃣''"""2⃣"""''3⃣""'

33"

'!" """ "#" "❹'What'is'TF'detecAon'sensiAvity?' '❺' '❻'

Contents'

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'''1⃣''Effects'

"of"transient"faults"

"""2⃣'"Threshold'

"of"a"soI"error"in"a"flip%flop"

"''3⃣""InjecAons'

"Simulate"transient"fault"currents"

DetecAon'SensiAvity'

❹'

35"

Data Register 1 Logic Block 1 Logic Block 2 Data Register 0

So\'Error'

Clock

Logic Block 0

Clock

Transient'Fault'

Integrated System

DetecAon'SensiAvity'

❹' Effects' 1⃣''"""2⃣"""''3⃣""'

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Logic Block 1 Logic Block 2 Data Register 0

No'So\'Error'

Clock

Logic Block 0

Clock

Transient'Fault'(Masked)'

Integrated System Data Register 0

DetecAon'SensiAvity'

❹' Effects' 1⃣''"""2⃣"""''3⃣""'

37"

Masked' Transient'Fault'

DetecAon'SensiAvity'

❹' Effects' 1⃣''"""2⃣"""''3⃣""'

Profile'of'

38"

Masked' Transient'Fault' So\'Error'

DetecAon'SensiAvity'

❹' Effects' 1⃣''"""2⃣"""''3⃣""'

Profile'of'

39"

Masked' Transient'Fault' So\'Error' Permanent'Effect'

DetecAon'SensiAvity'

❹' Effects' 1⃣''"""2⃣"""''3⃣""'

Profile'of'

40"

Masked' Transient'Fault' So\'Error' Permanent'Effect'

What'are'the'smallest' profiles'of'transient'faults' that'cause'a'so\'error?'

DetecAon'SensiAvity'

❹' Threshold' 1⃣''"""2⃣"""''3⃣""'

Profile'of'

41"

Masked' Transient'Fault' So\'Error' Permanent'Effect'

What'are'the'smallest' profiles'of'transient'faults' that'cause'a'so\'error?'

='

What'is'the'sensiAvity'of'a' memory'element'in' detecAng'transient'faults?'

DetecAon'SensiAvity'

❹' Threshold' 1⃣''"""2⃣"""''3⃣""'

Profile'of'

42"

DetecAon'SensiAvity'

Flip-Flop

Clock = 1 GHz 65-nm CMOS

❹' Threshold' 1⃣''"""2⃣"""''3⃣""'

43"

DetecAon'SensiAvity'

Flip-Flop

Clock = 1 GHz 65-nm CMOS

❹' Threshold' 1⃣''"""2⃣"""''3⃣""'

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Flip-Flop

Clock = 1 GHz 65-nm CMOS

IFaultP = ?

DetecAon'SensiAvity'

To'find'the'smallest' resulAng'in'so\'error'

❹'

tFall = ? IFaultP(t)

Threshold' 1⃣''"""2⃣"""''3⃣""'

45"

DetecAon'SensiAvity'

❹'

70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 0# 150# 300# 450# 600# 750# 900# 1050# 1200# 1350# 1500# 1650# 1800# 1950# 2100# #1_chain_of_4_inverters_flipflop#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

InjecAons' 1⃣''"""2⃣"""''3⃣""'

46"

70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 0# 150# 300# 450# 600# 750# 900# 1050# 1200# 1350# 1500# 1650# 1800# 1950# 2100# #1_chain_of_4_inverters_flipflop#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

DetecAon'SensiAvity'

Transient'fault'with'tFall'='150'ps' need'at'least'IFaultP'='175'μA'to' cause'a'so\'error'

❹' InjecAons' 1⃣''"""2⃣"""''3⃣""'

47"

'''1⃣''Effects'

"Masking,"soI"error,"or"permanent"effect"

"""2⃣'"Threshold'

"Between"masking"effect"and"soI"error"

"''3⃣""InjecAons'

"Curve"of"minimum"currents"detectable"by"flip%flop"

DetecAon'SensiAvity'

❹' Checklist' 1⃣''"""2⃣"""''3⃣""'

48"

'!" """ "#' "❹' '❺'Comparison'of'BBICS'architectures' '❻'

Contents'

49"

BBICS'

❺'

'''1⃣''Single' '''2⃣'"Single'LVT/HVT' '''3⃣""Zhang' '''4⃣'"Wirth'(IniAal)'' '''5⃣''New' '''6⃣''Modular"

50"

BBICS'

Single' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

Monitored Pull-Down Network Monitored Pull-Up Network

Flag ' Reset ' BulkN ' BulkP ' LATCH '

❺'

51"

BBICS'

Single' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

52"

BBICS'

Single' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

53"

Monitored Pull-Down Network Monitored Pull-Up Network

Flag ' Reset ' BulkN '

LVT ' HVT ' LVT ' HVT '

BulkP '

BBICS'

Single'LVT/HVT' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

LATCH '

❺'

54"

BBICS'

Single'LVT/HVT' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)# #1_chain_of_10_inverters_shsbbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

55"

BBICS'

Zhang' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

Monitored Pull-Up Network

Reset ' BulkP ' LATCH '

FlagP '

LVT ' HVT '

PMOS-BBICS

❺'

56"

NMOS-BBICS PMOS-BBICS

FlagN '

BBICS'

Zhang' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

Monitored Pull-Down Network Monitored Pull-Up Network

Reset ' BulkN ' BulkP ' LATCH '

FlagP '

LVT ' HVT '

❺'

57"

BBICS'

Zhang' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)# #1_chain_of_10_inverters_shsbbics#(PMOS)# #1_chain_of_10_inverters_zbbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

58"

BBICS'

Wirth'(IniAal)' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

Monitored Pull-Down Network Monitored Pull-Up Network

LATCH '

FlagN '

PMOS-BBICS

FlagP '

BulkP ' NMOS-BBICS

HVT ' LVT ' LVT ' HVT '

Reset '

LVT '

Reset '

LVT '

❺'

59"

BBICS'

Wirth'(IniAal)' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

Monitored Pull-Down Network Monitored Pull-Up Network

LATCH '

FlagN '

PMOS-BBICS

FlagP '

BulkP ' NMOS-BBICS

HVT ' LVT ' LVT ' HVT '

Reset '

LVT '

Reset '

LVT '

❺'

60"

BBICS'

Wirth'(IniAal)' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)# #1_chain_of_10_inverters_shsbbics#(PMOS)# #1_chain_of_10_inverters_zbbics#(PMOS)# #1_chain_of_10_inverters_bbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

61"

BBICS'

Tail Component (LATCH) ' BulkN '

Monitored Pull-Down Network

BulkP '

Monitored Pull-Up Network

New' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣' ❺'

62"

BBICS'

HVT ' LVT '

Tail Component (LATCH) '

LVT ' HVT '

BulkN '

Monitored Pull-Down Network

BulkP '

Monitored Pull-Up Network

New' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

15·Lmin " 15·Lmin "

❺'

63"

BBICS'

$ Upgrading its transient-fault sensitivity

15·Lmin "

HVT ' LVT '

Tail Component (LATCH) ' 15·Lmin "

LVT ' HVT '

BulkN '

Monitored Pull-Down Network

BulkP '

Monitored Pull-Up Network

New' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣' ❺'

64"

BBICS'

New' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)# #1_chain_of_10_inverters_shsbbics#(PMOS)# #1_chain_of_10_inverters_zbbics#(PMOS)# #1_chain_of_10_inverters_bbics#(PMOS)# #1_chain_of_10_inverters_t1hbbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

65"

BBICS'

BulkN '

Monitored Pull-Down Network

BulkP '

Monitored Pull-Up Network

Tail Component (LATCH) '

Modular' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣' ❺'

66"

BulkN_10 '

Monitored Pull-Down Network 10

BulkN_9 '

Monitored Pull-Down Network 9

BulkN_1 '

Monitored Pull-Down Network 1

BulkP_10 '

Monitored Pull-Up Network 10

BulkP_9 '

Monitored Pull-Up Network 9

BulkP_1 '

Monitored Pull-Up Network 1

BBICS'

Tail Component (LATCH) '

Modular' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣' ❺'

67"

BBICS'

Modular' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

110# 120# 130# 140# 150# 160# 170# 180# 190# 200# 210# 220# 230# 240# 250# 260# 50# 60# 70# 80# 90# 100# 110# 120# 130# 140# 150# 160# 170# 180# 190# #1_chain_of_4_inverters_flipflop#(PMOS)# #1_chain_of_10_inverters_sbbics#(PMOS)# #1_chain_of_10_inverters_t10hbbics#(PMOS)# #1_chain_of_10_inverters_shsbbics#(PMOS)# #1_chain_of_10_inverters_zbbics#(PMOS)# #1_chain_of_10_inverters_bbics#(PMOS)# #1_chain_of_10_inverters_t1hbbics#(PMOS)#

Fall#Time#of#Injected#Current#(ps)##

Minimum#Detectable#Amplitude#of#Injected#Current#(uA)#

❺'

68"

BBICS'

'''1⃣''Single:'the'least'detecAon'sensiAve' '''2⃣'"Single'LVT/HVT:'important'feature' '''3⃣""Zhang:'inefficient'extra'feedback'transistor' '''4⃣'"Wirth'(IniAal):'huge'power'consumpAon' '''5⃣''New:'the'most'transient7fault'detecAon'sensiAve' '''6⃣''Modular:'important'feature"

❺' Checklist' 1⃣'"""2⃣""''3⃣''''4⃣''''5⃣''''6⃣'

69"

"!" """ "#" "❹' '❺' '❻'Conclusions'

Contents'

70"

Conclusions'

'''1⃣''A'simulaAon'method'provides'a'metric' 'Compare'the'transient7fault'detecAon'sensiAvity'of'BBICS'architectures'

'IdenAfy'BBICS'features'that'produce'improvements'

'''2⃣'"A'new'BBICS'architecture'

'The'best'transient7fault'detecAon'sensiAvity' 'No'speed'degradaAon'and'negligible'power'consumpAon'overhead'

'''3⃣""Use'of'LVT'and'HVT'transistors'

'Improve'considerably'the'transient7fault'detecAon'sensiAvity'of'BBICS'

'''4⃣'"Modular'BBICS'technique'

'Ensure'a'compeAAve'area'overhead'

'''5⃣''Laser7based'test'of'BBICS'chip'

'Validate'BBICS'approach'on'CMOS'657nm'

❻'

71"

October 1st, 2014 – Palma de Mallorca, Spain.

Rodrigo'Possamai'Bastos*;'J.%M."Dutertre;"and"F."Sill"Torres;"

Comparison'of'Bulk'Built7In' Current'Sensors'(BBICS)'in'terms'of' Transient7Fault'DetecAon'SensiAvity'

72"

PT PTAP AP

P substrate N well P+

C"

• ut ‘1’

to Vdd

P+ N+ N+ N+ P+

to Gnd

in ‘0’

NMOS PMOS Metal 1 MOS gate

ionizing ion track

=> ‘0’

4"/"20"

73"

alarm flag

C"

• ut ‘1’

in ‘0’

PT PTAP AP

P substrate N well P+

to Vdd

P+ N+ N+ P+ NMOS PMOS

NMOS_bulk to Gnd BBICS"

Metal 1 MOS gate N+

5"/"20" to Gnd

74"

. . .' 10 ' . . .' 1'

ProtecAon'of'10'chains'of'10'inverters'by'

• ne'PMOS7BBICS'and'one'NMOS7BBICS'

(a'commercial'657nm'CMOS'Technology)"

PMOS-BBICS Flag FlagN FlagP NMOS-BBICS

Reference'Circuit'

IFaultN