Comparison'of'Bulk'Built7In' Current'Sensors'(BBICS)'in'terms'of' Transient7Fault'DetecAon'SensiAvity' Rodrigo'Possamai'Bastos*;' J.%M."Dutertre;"and"F."Sill"Torres;" October 1st, 2014 – Palma de Mallorca, Spain. 1"
Outline' ' ! ' Context:'transient'fault'(TF)'effects " " " " OpAmized'miAgaAon'soluAons " " # " OperaAon'mode'of'a 'BBICS' " ❹ " What'is'TF'detecAon'sensiAvity?' ' ❺' Comparison'of'BBICS'architectures' ' ❻ ' Conclusions' 2"
Physical'limits' Process'variability' Low'voltage'levels' 90 nm System'complexity' High'frequencies' 65 nm 28 nm Microscope'image'of'a'nanocircuit'(IBM,'2010)' 3"
Transient'fault'effects'on'ICs' " " "Reliability "" " " "Fault"Tolerance" " " " "Security" " " " 4"
Natural Sources Environmental Perturbations Artificial Sources Even'at'ground'level'!' Transient'Faults' 5"
Intentional Good Encryption Results ! ! ' Perturbations D F A ' Versus Faulty Encryption Results Laser ' Outputs ! ! Secret Key Transient'Faults' Inputs Input Word 6"
Transient'Fault'(e.g.'SET)' Integrated System Register 0 Register 1 Data Data Logic Logic Logic Block 0 Block 1 Block 2 Clock Clock Indirect' So\'Error' (e.g.'SEU)' 7"
Transient'Fault'(e.g.'SET)' Integrated System Register 0 Register 1 Data Data Logic Logic Logic Block 0 Block 1 Block 2 Clock Clock Direct' So\'Error' (e.g.'SEU)' 8"
! ' Transient'Faults' Checklist' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ' ''1 ⃣ '' Nano7systems' " More"sensiCve"to"transient"faults" " "" 2 ⃣ ' " Origin' " Environmental"or"intenConal"sources" " ''3 ⃣ "" Logical'effects' " Indirect"or"direct"soI"errors" 9"
Contents' " ! " " " " OpAmized'miAgaAon'soluAons " " # " " ❹ ' ' ❺ ' ' ❻ ' 10"
" ' MiAgaAon'soluAons' ' ''1 ⃣ '' Strategy' "For"miCgaCon"of"transient"faults " " "" 2 ⃣ ' " TradiAonal' "DetecCon"techniques" " ''3 ⃣ "" BICS' "Built%In"Current"Sensors" 11"
" ' MiAgaAon'soluAons' Strategy' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Integrated System’s Block Register Logic Block Clock 12"
" ' MiAgaAon'soluAons' Strategy' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Integrated System’s Block Register Logic Block Clock Concurrent Error Detection Circuitry fault_flag_signal 13"
" ' MiAgaAon'soluAons' Strategy' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Integrated System’s Block Register Logic Block Clock Concurrent Error Detection Circuitry fault_flag_signal System’s System’s System’s or or Restart Recovery Deadlock Alternatives of Actions after Detection 14"
" ' MiAgaAon'soluAons' TradiAonal' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Duplication with Comparison (DWC) Logic Register Data Block Clock 15"
" ' MiAgaAon'soluAons' TradiAonal' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Duplication with Comparison (DWC) Logic Register Data Block Clock Comparator Result Redundant Register Copy of 1 Logic Block Clock N 16"
" ' MiAgaAon'soluAons' TradiAonal' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ☹ Area overhead > 2x Duplication with Comparison (DWC) Time Redundancy (TR) Logic Logic Register Register Data Block Block Data Clock Clock Comparator Result Redundant Register Copy of 1 Logic Block Clock N 17"
" ' MiAgaAon'soluAons' TradiAonal' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ☹ Area overhead > 2x ☹ High delay degradation Duplication with Comparison (DWC) Time Redundancy (TR) Logic Logic Register Register Data Block Block Data Clock Clock Comparator Comparator Result Result Delay Redundant Redundant Register Copy of Register 1 1 Logic Block Clock Clock N N 18"
" ' MiAgaAon'soluAons' TradiAonal' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Built-In Current Sensor (BICS) Logic Register Data Block Clock $ Much smaller than DWC $ More efficient than TR Result Register BICS Fault 1 1 Duplication with Comparison (DWC) Time Redundancy (TR) Logic Logic Register Register Data Block Block Data Clock Clock Comparator Comparator Result Result Delay Redundant Redundant Register Copy of Register 1 1 Logic Block Clock Clock N N 19"
" ' MiAgaAon'soluAons' BICS' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' VBICS FlagP PMOS-VBICS NMOS-VBICS FlagN BICS at V DD and V SS ' 20"
" ' MiAgaAon'soluAons' BICS' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' VBICS FlagP = 0 ON ' PMOS-VBICS 0 ' 1 ' ' OFF NMOS-VBICS FlagN = 0 BICS at V DD and V SS ' 21"
" ' MiAgaAon'soluAons' BICS' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' VBICS FlagP = 0 ON ' PMOS-VBICS 0 ' 1 " 0 ' Alarm I fault Flag ' OFF NMOS-VBICS FlagN = 1 BICS at V DD and V SS ' 22"
" ' MiAgaAon'soluAons' BICS' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ☹ Delay degradation $ No delay degradation ☹ Detection of legal transitions $ Detection of only illegal transitions VBICS ? FlagP PMOS-VBICS NMOS-VBICS FlagN BICS at V DD and V SS ' 23"
" ' MiAgaAon'soluAons' BICS' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ☹ Delay degradation $ No delay degradation ☹ Detection of legal transitions $ Detection of only illegal transitions VBICS BBICS FlagP PMOS-VBICS FlagP PMOS-BBICS NMOS-BBICS FlagN NMOS-VBICS FlagN BICS at V DD and V SS BICS at Bulk (body-ties) ' ' 24"
" ' MiAgaAon'soluAons' Checklist' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ' ''1 ⃣ '' Strategy' " Error"detecCon"+"CorrecCon"AcCon" " "" 2 ⃣ ' " TradiAonal' " DuplicaCon"(+Area);"Time"Redundancy"(+Speed)" " ''3 ⃣ "" BICS' " VBICS"(%Efficiency);"BBICS"(=Speed,"+Efficiency)" 25"
Contents' ' ! " " " " " # " OperaAon'mode'of 'a'BBICS' " ❹ ' ' ❺ ' ' ❻ ' 26"
# ' BBICS'OperaAon' ' ''1 ⃣ '' Register' "IndicaCon"of"fault " " "" 2 ⃣ ' " ConnecAons' "BBICS"to"monitored"gates" " ''3 ⃣ "" AmplificaAon' "Anomalous"transient"current" 27"
# ' BBICS'OperaAon' Register' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' LATCH ' ' Flag ' Reset 28"
# ' BBICS'OperaAon' ConnecAons' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Monitored Pull-Up Network ' BulkP LATCH ' ' Flag ' Reset 29"
# ' BBICS'OperaAon' ConnecAons' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Monitored Pull-Up Network ' BulkP LATCH ' ' Flag ' Reset ' BulkN Monitored Pull-Down Network 30"
# ' BBICS'OperaAon' AmplificaAon' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Monitored Pull-Up Network ' BulkP V th X p · W min " LATCH ' ' Flag ' Reset " X n · W min V th ' BulkN Monitored Pull-Down Network 31"
# ' BBICS'OperaAon' Checklist' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' ' ''1 ⃣ '' Register' " Asynchronous"latch"to"memorize"fault"flag" " "" 2 ⃣ ' " ConnecAons' " High%ohmic"and"pull%up"(and"%down)"transistors" " ''3 ⃣ "" AmplificaAon' " Transistor"sizing:"lower"Vth,"higher"detecCon" 32"
Contents' ' ! " " " " " # " " ❹' What'is'TF'detecAon'sensiAvity?' ' ❺ ' ' ❻ ' 33"
DetecAon'SensiAvity' ❹' ' ''1 ⃣ '' Effects' "of"transient"faults " " "" 2 ⃣ ' " Threshold' "of"a"soI"error"in"a"flip%flop" " ''3 ⃣ "" InjecAons' "Simulate"transient"fault"currents" 34"
DetecAon'SensiAvity' Effects' ❹' 1 ⃣ '' """ 2 ⃣ """ ''3 ⃣ "" ' Transient'Fault' Integrated System Register 0 Register 1 Data Data Logic Logic Logic Block 0 Block 1 Block 2 Clock Clock So\'Error' 35"
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