Chengxin Zhao chengxin.zhao@impcas.ac.cn Institute of Modern - - PowerPoint PPT Presentation

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Chengxin Zhao chengxin.zhao@impcas.ac.cn Institute of Modern - - PowerPoint PPT Presentation

Aug 27, 2022 245 likes •457 views

Electronics of the Pixel and Silicon Strip Detectors at HIRFL and HIAF Chengxin Zhao chengxin.zhao@impcas.ac.cn Institute of Modern Physics Chinese Academy of Science 9 th PIXEL, December 10-14, 2018 1 Two cyclotrons SFC (K = 69) and SSC

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Electronics of the Pixel and Silicon Strip Detectors at HIRFL and HIAF

Chengxin Zhao

Institute of Modern Physics Chinese Academy of Science 9th PIXEL, December 10-14, 2018

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chengxin.zhao@impcas.ac.cn

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  • Two cyclotrons SFC (K = 69) and SSC (K = 450) for beam injection
  • CSRm: Heavy ions will be accumulated, cooled and accelerated
  • CSRe: High sensitive & accuracy (~10E-6) spectrometer and deacceleration
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The External Target Facility

  • Study equation of state of nuclear matter, radioactive ion beams and hyper

nuclear.

  • The SSD identifies medium-weight fragments through ΔE-E methodology
  • Contains 12 telescopes, each of which has two double-sided silicon strip arrays.
  • Each array is 5cm x 5cm and has 96 strips on both sides
  • In total the silicon strip detector has 4608 detector pads.
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SLIDE 4

The Internal Target Facility

  • Beam is ejected into the ring and bombards the

gas-jet target.

  • Light recoils will be scattered at large angle,

and the beam-like fragments will go forward with a small angle.

  • The recoil detector measures scattering target-

like particles. The downstream detector is used for coincidence measurements.

  • Detectors consists of silicon pixel detector and

silicon strip detectors

  • PIXEL/SSD: Energy loss and scattering angle
  • SSD: for measuring residual energy of the particles.

From Ke Yue (IMP, CAS)

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The Silicon Strip Detector

5cm x 5cm Double-Side 16 Strips 5cm x 5cm Double-Side 96 Strips Energy Resolution ~1%

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The SSD – Front-end Electronics

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SLIDE 7

High Intensity Heavy-ion Accelerator Facility (HIAF)

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  • A high current superconducting linac (iLinac)
  • 34 Tm synchrotron (BRing) equipped with electron cooling for beam accumulation
  • Multifunction experimental storage ring (SRing)
  • 43 Tm synchrotron (CRing) for beam compression and stacking
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SLIDE 8

Electron Ion Collider in China (EicC)

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From Yutie Liang (IMP, CAS)

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18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

13th 5-year plan 14th 5-year plan 15th 5-year plan 16th 5-year plan

HIAF

EicC-I R&D

√s ~ 15 GeV, 1x1033/sec cm2

R&D and construction In operation

  • Nucleon Structure (sea quark): 1D PDF, GPD, TMD
  • Hadron spectroscope
  • Proton mass

Facilities Main goals JLab 12 GeV JLab 12 GeV Valence quark Valence quark EicC EicC-I Valence and Sea quark Valence and Sea quark US and Europe EIC Gluon Gluon

From Xurong Chen (IMP, CAS)

EicC Phyiscs Goal

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SLIDE 10

EicC Conceptual Detector System

Vertex(pixel) TPC GEM GEM DIRC + TOF EMcal (Sci-Fi/Shaslyk)

Solenoid coil Flux return yoke

Disk DIRC EMcal(Shaslyk)

GEM

EMcal(PWO4) EMcal(Shaslyk + PWO4 Disk DIRC

Flux return coils Flux return coils HCal HCal

ion e

EMCal Pixel VTX ToF COIL TPC i-forward system e-forward system

C C

Detector design and simulation in very early stage

  • Vertex detector -> Identify event vertex, secondary vertices, track impact parameters (Pixel)
  • Central tracker -> Measure charged track momenta (TPC)
  • Forward tracker -> Measure charged track momenta (GEMs)
  • Particle Identification -> pion, kaon, proton separation TOF + DIRC
  • EMCal -> Measure photons (E, angle), identify electrons (Shashlik or Sci-FI detector)

From Xurong Chen (IMP, CAS)

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The Vertex Detector

⚫ Vertex detector -> Identify event vertex, secondary vertices, track impact parameters ⚫ Important for heavy flavor physics ⚫ Impact of spatial resolution has been simulated Pythia-6428 D0→K-π+ (PID: 100% ) Sig 30%, bkg 6% Sig 30%, bkg 2% ⚫ Very preliminary simulation shows 20um (at least) resolution is needed. ⚫ Refer to the ALICE ITS / CEPC detector, possibly ~5um resolution is needed. From Yutie Liang (IMP, CAS)

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The MAPS – protype design

⚫ Chip size 2.5 cm x 1.5 cm Pixel Size 60 cm x 60 um ⚫ Pixels：215 x 400，total size: 2.4 cm x 1.29 cm ⚫ Design with 130nm Huahong process with STI ⚫ Spatial Resolution better than 20um ⚫ Integration time < 10 us（peaking < 2 μs，duration < 8 μs） ⚫ Dynamic range（Comparator 2K，Liner range 2K~4K，Output Amplitude (150mV~750mV） ⚫ Noise <15 e- (Amp noise < 13 e- and mismatch < 2 e-)。 ⚫ Power consumption < 1W ⚫ Tape out at June 2019 Photo-Diode and Reset Charge Sensitive Amplifier Comparator and THR (DAC + Radhard SRAM)

From Xiangming Sun (CCNU)

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Topmetal – Possible Innovation for TPC

8800µm 9100µm 6000µm 6000µm

⚫ Pixel array 72×72. ⚫ Pixel size 83.2um*83.2um. ⚫ TopMetal size 25um*25um ⚫ Chip noise 13.9e-

  • Less charge diffusion and short drifting Distance
  • Reduce the size and increase the readout speed of TPC

From Xiangming Sun (CCNU)

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Topmetal – Possible Innovation for TPC

  • First Prototype has been validated at HIRFL Terminal in LanZhou
  • 25 MeV/u Kr, LET 20.05 MeV/(mg/cm2)

The Topmetal

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SLIDE 15

Pixel - Front-end Electronics

⚫ Versatile platform

  • Digital -> SFP tranceiver (1.25/2.5/5Gbps)
  • Analog -> LEMO port
  • Provide clock, power, etc. to DUT

⚫ USB interface -> Control and backup ⚫ For high radaition environment

  • Flash-based Main FPGA
  • SF2 proven to be stable in ALICE TPC (Run2)
  • TMR on vital modules in the firmware

⚫ For high vacuum condition

  • Proven to be stable with 1.0×10E-2 mbar

⚫ Current monitoring

  • Power cycle after 10ms
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The Prototype Readout Electronics

  • The HAIF/HIRFL Common Readout Unit (HCRU)

⚫ 6U PXI standard

– Compatible to the present HIRFL-CSR facility

⚫ General Differentail Digital IO

– 32 pair input, 16 pair ouptut

⚫ Analog IO

– 8 channel, 14-bit ADC – 8 channel, 16-bit DAC

⚫ Two Fiber transmision links

– 1.25/2.5/5Gbps

⚫ 1GbE Link

– Control and Monitoring

⚫ USB serial communication ⚫ Prototype for irradiation test ⚫ Irradiation test will be at HIRFL (heavy ion) and China Spallation Neutron Source (Neutron)

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The HCRU Firmware design

⚫ FPGA design is in finalizing phase

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Summary and Outlook

⚫ Silicon Strip detector for HIRFL achieves the energy resolution of ~1%. ⚫ MAPS with the size of 2.5cm x 1.5 cm and the resolution of ~20um has been designed for EicC ⚫ Prototype of the Topmetal pixel has been validated to a possible alternative for TPC. ⚫ A versatile test platform - HCRU has been design for the R&D of pixel and silicon strip detectors ⚫ Hardware of HCRU has been proven to be stable. ⚫ Firmware of HCRU is in finalizing phase. ⚫ Irradiation test will be performed at HIRFL (heavy ion) and CSNS (Neutron)

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Thanks for attention! Nice trip back home!

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The Test – Solution II

The CDAU – Common Data Aggregation Unit

  • Configuration monitoring & management: • Onboard

storage for multiple configurations • Monitor and retrigger configuration process even if PCIe link is down • Firmware upgrade via PCIe • FPGA configuration within less than 100 ms • Custom scatter-gather DMA engi channels • Host side: Microdriver with userspa Online data preprocessing: TPC FastClusterFind DDR3 tested up to 2x 8GB DDR3 SO-DIMM modules • PCIe throughput: ~3400 MB/s (SandyBridge) • Reusing existing fiber installation with break-out fibers and compatible QSFP transceivers

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The RCU Firmware design