Chapter 6 Design Organization and Parameterization Part 3 1 - - PowerPoint PPT Presentation

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Chapter 6 Design Organization and Parameterization Part 3 1 - - PowerPoint PPT Presentation

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Chapter 6 Design Organization and Parameterization Part 3 1 benyamin@mehr.sharif.edu Design Parameterzing To make general models usable in different designs The specific behavior of model is dependent on the parameters that are

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Chapter 6

Design Organization and Parameterization Part 3

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Design Parameterzing

  • To make general models usable in

different designs

  • The specific behavior of model is

dependent on the parameters that are determined by the design entities that use them

  • Communicating nonhardware and

nonsignal information between designs

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Generic Syntax

GENERIC ( interface_constant_declarations );

  • GENERIC clause is used before PORT cluase in ENTITY

declaration

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Generic Example

ENTITY inv IS GENERIC(tplh:TIME:= 5 ns; tphl:TIME:=3 ns ); PORT (i1: IN BIT;o1:OUT BIT); END; ARCHITECTURE av OF inv IS BEGIN

  • 1<=NOT i1 AFTER (tplh+tphl)/2;

END;

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Using Generic in Components

G0:ENTITY WORK.inv GENERIC MAP( 3 ns, 4 ns) PORT MAP(a,z); G1:ENTITY WORK.inv PORT MAP(x,y); --using default values ENTITY c IS GENERIC (t1:IN TIME;t2:IN TIME) PORT(…); END; ARCHITECTURE x OF c IS … BEGIN comp0:ENTITY WORK.inv GENERIC MAP(t1,t2) PORT MAP(a,z); END;

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Named Association

  • Actual parameters can be used in Named

Association manner

G0:ENTITY WORK.inv GENERIC MAP(tplh=> 3 ns,tphl=> 4 ns) PORT MAP(o1=>a,i1=>z);

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OPEN Actual Parameter

  • Outputs can be associate with OPEN

signal

  • Inputs can be open when they have

default values.

G0:ENTITY WORK.inv GENERIC MAP(tplh=> 3 ns,tphl=> OPEN) PORT MAP(o1=>OPEN,i1=>z);

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IEEE 1164 std_logic Type

std_logic Values

Don’t Care Weak 0 Weak 1 Weak Unknown High Impedance One Zero Conflict – Forcing Unknown Uninitialized X

  • H

L W Z 1 U U U U U U U U U U X X X X X X

  • X

1 X X 1 X H L X X X X X X W X X X X X X Z X 1 X X 1 X 1 X X X X X X X U U U U U U U U

  • H

L W Z 1 X

std_logic AND Table

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IEEE 1164 Types

  • Std_logic is a resolved type
  • Std_logic_vector is array of std_logic
  • To use this types, ieee library must be defined in

top of your entity. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;

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std_logic Usage Example

LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY Adder IS PORT (a,b,Cin:IN std_logic; z,Cout:OUT std_logic:=‘Z’ ); END;

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Std_logic Resolution Table

U U U U U U U U U U X X X X X X X X X X X

  • X

H W W H 1 X H L X W L W L X X W W W W 1 X W X H L W Z 1 X Z X 1 1 1 1 1 X X 1 X X X X X X X X X U U U U U U U U U

  • H

L W Z 1 X

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Design Configuration

  • Binding a component instantiation to an actual

component does not have to be done in the architecture

  • It is possible to generate a generic design and

specify the details of timing or a specific component library at later stage

  • A single test bench can be used to test various

versions of the same component

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General Purpose Test Bench

ENTITY Test IS END; ARCHITECTURE func OF test IS COMPONENT comp1 IS PORT(a,b:IN BIT_VECTOR(3 downto 0); gt,eq,lt: IN BIT; a_gt_b,a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL a,b,gtr,less,eql:BIT; BEGIN c: comp1 PORT MAP (a,b,’0’,’1’,’0’,gtr,eql,lss); a<=“0000”,”1111” AFTER 50 ns, “1110” AFTER 150 ns; b<=“0000”,”1110” AFTER 50 ns, “1111” AFTER 150 ns; END;

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Configuration for Testing - 1

USE WORK.ALL; CONFIGURATION functional OF test IS FOR func FOR c: comp1

USE ENTITY WORK.nibble_comparator(structural);

END FOR; END FOR; END functional;

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Configuration for Testing - 2

USE WORK.ALL; CONFIGURATION functional OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative); END FOR; END FOR; END functional;

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Configuration Declaration Syntax

CONFIGURATION conf_name OF entity_name IS FOR block_name { component_configuration | block_configuration } END FOR; END;

Block_configuration

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Configuring Nested Components

USE WORK.comp_lib.ALL; Architecture iterative1 OF nibble_comparator IS SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END;

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Configuring Nested Components

USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1

USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(default_delay); FOR c1toc2 FOR c: USE ENTITY WORK.bit_comparator(single_delay); END FOR; END FOR; END FOR; END FOR; END;

Test Nibble_comparator Bit_comparator block_declarations

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Configuring Nested Components

USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(fixed_delay); FOR c1toc2 FOR c: USE ENTITY WORK.bit_comparator(fixed_delay); END FOR; END FOR; END FOR; END FOR; END;

block_declarations

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Generic Parameter Specification

USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(fixed_delay) GENERIC MAP(2 NS,4 NS); FOR c1toc2 FOR c: USE ENTITY WORK.bit_comparator(fixed_delay) GENERIC MAP(4 NS,6 NS); END FOR; END FOR; END FOR; END FOR; END;

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Incremental Binding

  • Complete binding is partly done in a

configuration specification and partly done in a configuration declaration

  • The original bindings is referred to as

primary binding indications

  • Incremental binding indications either

complement or overwrite primary binding indications

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Primary Binding Indication

Architecture iterative1 OF nibble_comparator IS COMPONENT comp1 IS PORT(a,b, gt,eq,lt: IN BIT; a_gt_b,a_eq_b,a_lt_b : OUT BIT); END COMPONENT;

FOR ALL: comp1 USE ENTITY WORK.bit_comparator(passed_delay);

SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END;

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Incremental Binding Indication

USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 GENERIC MAP(2 NS,4 NS); FOR c1toc2 FOR c: USE ENTITY WORK.bit_comparator(fixed_delay) GENERIC MAP(4 NS,6 NS); END FOR; END FOR; END FOR; END FOR; END;

Overwrites primary binding Uses primary binding

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Binding

Architecture iterative1 OF nibble_comparator IS COMPONENT comp1 IS PORT(a,b, gt,eq,lt: IN BIT; a_gt_b,a_eq_b,a_lt_b : OUT BIT); END COMPONENT;

FOR ALL: comp1 USE CONFIGURATION WORK.struct;

SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END;

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Parity Example – XOR Component

ENTITY xor2_t IS GENERIC(tplh:TIME:=9 ns;tphl:TIME:1 ns); PORT(i1,i2: IN std_logic;o1:OUT std_logic); END; ARCHITECTURE average_delay OF xor2_t IS BEGIN

  • 1<=i1 XOR i2 AFTER (tplh+tphl)/2;

END;

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Parity Example – INV Component

ENTITY inv_t IS GENERIC(tplh:TIME:=9 ns;tphl:TIME:1 ns); PORT(i1: IN std_logic;o1:OUT std_logic); END; ARCHITECTURE average_delay OF inv_t IS BEGIN

  • 1<= NOT i1 AFTER (tplh+tphl)/2;

END;

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Parity Circuit

ENTITY parity IS PORT(a: IN std_logic_vector(7 downto 0);

  • dd,even:OUT std_logic);

END; ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT(i1,i2: IN std_logic;o1:OUT std_logic); COMPONENT n1 PORT(i1: IN std_logic;o1:OUT std_logic); SIGNAL im:std_logic_vector(0 TO 6); BEGIN first: x2 PORT MAP(a(0),a(1),im(0)); middle: FOR i IN 1 to 6 GENERATE m: x2 PORT MAP (im(i-1),a(i+1),im(i)); END GENERATE; last:odd <= im(6); inv: n1 PORT MAP(im(6),even); END;

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Parity Configuration Declaration

CONFIGURATION parity_binding OF parity IS FOR iterative FOR first: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP(5 NS, 5 NS); END FOR; FOR middle(1 TO 5) FOR m: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP(5 NS, 5 NS); END FOR; END FOR; FOR middle(6) FOR m: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP(6 NS, 7 NS); END FOR; END FOR; FOR inv: n1 USE ENTITY WORK.inv_t(average_delay) GENERIC MAP(5 NS, 5 NS); END FOR; END FOR; END ;