Chapter 6 Design Organization and Parameterization Part 3 1 - PowerPoint PPT Presentation

Chapter 6 Design Organization and Parameterization Part 3 1 benyamin@mehr.sharif.edu

Design Parameterzing • To make general models usable in different designs • The specific behavior of model is dependent on the parameters that are determined by the design entities that use them • Communicating nonhardware and nonsignal information between designs 2 benyamin@mehr.sharif.edu

Generic Syntax GENERIC ( interface_constant_declarations ); •GENERIC clause is used before PORT cluase in ENTITY declaration 3 benyamin@mehr.sharif.edu

Generic Example ENTITY inv IS GENERIC(tplh:TIME:= 5 ns; tphl:TIME:=3 ns ); PORT (i1: IN BIT;o1:OUT BIT); END; ARCHITECTURE av OF inv IS BEGIN o1<=NOT i1 AFTER (tplh+tphl)/2; END; 4 benyamin@mehr.sharif.edu

Using Generic in Components G0:ENTITY WORK.inv GENERIC MAP( 3 ns, 4 ns) PORT MAP(a,z); G1:ENTITY WORK.inv PORT MAP(x,y); --using default values ENTITY c IS GENERIC (t1:IN TIME;t2:IN TIME) PORT(…); END; ARCHITECTURE x OF c IS … BEGIN comp0:ENTITY WORK.inv GENERIC MAP(t1,t2) PORT MAP(a,z); END; 5 benyamin@mehr.sharif.edu

Named Association • Actual parameters can be used in Named Association manner G0:ENTITY WORK.inv GENERIC MAP(tplh=> 3 ns,tphl=> 4 ns) PORT MAP(o1=>a,i1=>z); 6 benyamin@mehr.sharif.edu

OPEN Actual Parameter • Outputs can be associate with OPEN signal • Inputs can be open when they have default values. G0:ENTITY WORK.inv GENERIC MAP(tplh=> 3 ns,tphl=> OPEN) PORT MAP(o1=>OPEN,i1=>z); 7 benyamin@mehr.sharif.edu

IEEE 1164 std_logic Type std_logic Values std_logic AND Table U Uninitialized U X 0 1 Z W L H - Conflict – Forcing U U U 0 U U U U U U X Unknown X U X 0 X X X 0 X X 0 Zero 0 0 0 0 0 0 0 0 0 0 1 One 1 U X 0 1 X X 0 1 X Z High Impedance Z U X 0 X X X 0 X X W Weak Unknown W U X 0 X X X 0 X X L Weak 1 L U 0 0 0 0 0 0 0 0 H Weak 0 H U X 0 1 X X 0 1 X - Don’t Care - U X 0 X X X 0 X X 8 benyamin@mehr.sharif.edu

IEEE 1164 Types • Std_logic is a resolved type • Std_logic_vector is array of std_logic •To use this types, ieee library must be defined in top of your entity. LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; 9 benyamin@mehr.sharif.edu

std_logic Usage Example LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY Adder IS PORT (a,b,Cin:IN std_logic ; z,Cout:OUT std_logic:=‘Z’ ); END; 10 benyamin@mehr.sharif.edu

Std_logic Resolution Table U X 0 1 Z W L H - U U U U U U U U U U X U X X X X X X X X 0 U X 0 X 0 0 0 0 X 1 U X X 1 1 1 1 1 X Z U X 0 1 Z W L H X W U X 0 1 W W W W X L U X 0 0 L W L W X H U X 0 1 H W W H X - U X X X X X X X X 11 benyamin@mehr.sharif.edu

Design Configuration • Binding a component instantiation to an actual component does not have to be done in the architecture • It is possible to generate a generic design and specify the details of timing or a specific component library at later stage • A single test bench can be used to test various versions of the same component 12 benyamin@mehr.sharif.edu

General Purpose Test Bench ENTITY Test IS END; ARCHITECTURE func OF test IS COMPONENT comp1 IS PORT(a,b:IN BIT_VECTOR(3 downto 0); gt,eq,lt: IN BIT; a_gt_b,a_eq_b, a_lt_b : OUT BIT); END COMPONENT; SIGNAL a,b,gtr,less,eql:BIT; BEGIN c: comp1 PORT MAP (a,b,’0’,’1’,’0’,gtr,eql,lss); a<=“0000”,”1111” AFTER 50 ns, “1110” AFTER 150 ns; b<=“0000”,”1110” AFTER 50 ns, “1111” AFTER 150 ns; END; 13 benyamin@mehr.sharif.edu

Configuration for Testing - 1 USE WORK.ALL; CONFIGURATION functional OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(structural ); END FOR; END FOR; END functional; 14 benyamin@mehr.sharif.edu

Configuration for Testing - 2 USE WORK.ALL; CONFIGURATION functional OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative); END FOR; END FOR; END functional; 15 benyamin@mehr.sharif.edu

Configuration Declaration Syntax CONFIGURATION conf_name OF entity_name IS FOR block_name { component_configuration | Block_configuration block_configuration } END FOR; END; 16 benyamin@mehr.sharif.edu

Configuring Nested Components USE WORK.comp_lib.ALL; Architecture iterative1 OF nibble_comparator IS SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END; 17 benyamin@mehr.sharif.edu

Configuring Nested Components USE WORK.ALL; Test CONFIGURATION default OF test IS FOR func FOR c: comp1 Nibble_comparator USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 Bit_comparator FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(default_delay); FOR c1toc2 FOR c: USE ENTITY block_declarations WORK.bit_comparator(single_delay); END FOR; END FOR; END FOR; END FOR; END; 18 benyamin@mehr.sharif.edu

Configuring Nested Components USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(fixed_delay); FOR c1toc2 FOR c: USE ENTITY block_declarations WORK.bit_comparator(fixed_delay); END FOR; END FOR; END FOR; END FOR; END; 19 benyamin@mehr.sharif.edu

Generic Parameter Specification USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); FOR iterative1 FOR c0,c3: comp1 USE ENTITY WORK.bit_comparator(fixed_delay) GENERIC MAP(2 NS,4 NS); FOR c1toc2 FOR c: USE ENTITY WORK.bit_comparator(fixed_delay ) GENERIC MAP(4 NS,6 NS); END FOR; END FOR; END FOR; END FOR; END; 20 benyamin@mehr.sharif.edu

Incremental Binding • Complete binding is partly done in a configuration specification and partly done in a configuration declaration • The original bindings is referred to as primary binding indications • Incremental binding indications either complement or overwrite primary binding indications 21 benyamin@mehr.sharif.edu

Primary Binding Indication Architecture iterative1 OF nibble_comparator IS COMPONENT comp1 IS PORT(a,b, gt,eq,lt: IN BIT; a_gt_b,a_eq_b,a_lt_b : OUT BIT); END COMPONENT; FOR ALL: comp1 USE ENTITY WORK.bit_comparator(passed_delay); SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END; 22 benyamin@mehr.sharif.edu

Incremental Binding Indication USE WORK.ALL; CONFIGURATION default OF test IS FOR func FOR c: comp1 USE ENTITY WORK.nibble_comparator(iterative1); Uses FOR iterative1 primary FOR c0,c3: comp1 GENERIC MAP(2 NS,4 NS); binding FOR c1toc2 FOR c: Overwrites USE ENTITY primary WORK.bit_comparator(fixed_delay) GENERIC MAP(4 NS,6 NS); binding END FOR; END FOR; END FOR; END FOR; END; 23 benyamin@mehr.sharif.edu

Binding Architecture iterative1 OF nibble_comparator IS COMPONENT comp1 IS PORT(a,b, gt,eq,lt: IN BIT; a_gt_b,a_eq_b,a_lt_b : OUT BIT); END COMPONENT; FOR ALL: comp1 USE CONFIGURATION WORK.struct; SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN c0:comp1 PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:comp1 PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:comp1 PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b); END; 24 benyamin@mehr.sharif.edu

Parity Example – XOR Component ENTITY xor2_t IS GENERIC(tplh:TIME:=9 ns;tphl:TIME:1 ns); PORT(i1,i2: IN std_logic;o1:OUT std_logic); END; ARCHITECTURE average_delay OF xor2_t IS BEGIN o1<=i1 XOR i2 AFTER (tplh+tphl)/2; END; 25 benyamin@mehr.sharif.edu

Parity Example – INV Component ENTITY inv_t IS GENERIC(tplh:TIME:=9 ns;tphl:TIME:1 ns); PORT(i1: IN std_logic;o1:OUT std_logic); END; ARCHITECTURE average_delay OF inv_t IS BEGIN o1<= NOT i1 AFTER (tplh+tphl)/2; END; 26 benyamin@mehr.sharif.edu

Parity Circuit ENTITY parity IS PORT(a: IN std_logic_vector(7 downto 0); odd,even:OUT std_logic); END; ARCHITECTURE iterative OF parity IS COMPONENT x2 PORT(i1,i2: IN std_logic;o1:OUT std_logic); COMPONENT n1 PORT(i1: IN std_logic;o1:OUT std_logic); SIGNAL im:std_logic_vector(0 TO 6); BEGIN first: x2 PORT MAP(a(0),a(1),im(0)); middle: FOR i IN 1 to 6 GENERATE m: x2 PORT MAP (im(i-1),a(i+1),im(i)); END GENERATE; last:odd <= im(6); inv: n1 PORT MAP(im(6),even); END; 27 benyamin@mehr.sharif.edu

Parity Configuration Declaration CONFIGURATION parity_binding OF parity IS FOR iterative FOR first: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP(5 NS, 5 NS); END FOR; FOR middle(1 TO 5) FOR m: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP( 5 NS, 5 NS ); END FOR; END FOR; FOR middle(6) FOR m: x2 USE ENTITY WORK.xor2_t(average_delay) GENERIC MAP( 6 NS, 7 NS ); END FOR; END FOR; FOR inv: n1 USE ENTITY WORK.inv_t(average_delay) GENERIC MAP(5 NS, 5 NS); END FOR; END FOR; END ; 28 benyamin@mehr.sharif.edu