Chapter 6: Digital Data Communication Techniques
Sequence 6 Page 1 CS420/520 Axel Krings
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Chapter 6: Digital Data Communication Techniques CS420/520 Axel Krings Page 1 Sequence 6 Asynchronous and Synchronous Transmission Timing problems require a mechanism to synchronize the transmitter and receiver Two solutions
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— One bit altered — Adjacent bits not affected
— Length B — Contiguous sequence of B bits in which first, last and any number of intermediate bits are in error — Impulse noise — Fading in wireless — Effect is greater at higher data rates
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bits corrupted by error Sent Received burst error of length B = 10 single-bit error
0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1
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transmitted frame
— Data transmitted as one or more contiguous sequences of bits
bit error increases
— The longer the frame, the more bits it has and the higher the probability that one of these is in error
Pb
rate (BER)
P1
P2
with one or more undetected errors
P3
with one or more detected bit errors but no undetected bit errors
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E = f(data)
k bits data data data'
E' = f(data') COMPARE
n – k bits n bits
Figure 6.2 Error Detection Process Transmitter Receiver
E, E' = error-detecting codes f = error-detecting code function
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– 00000 00111 11100 11011
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b1,1 b1,j row parity column parity r1
Figure 6.3 A Two-Dimensional Even Parity Scheme
b2,1 b2,j r2 bi,1 bi,j ri c1 cj p
(a) Parity calculation (b) No errors
0 1 1 1 0 1 0 1 1 1 0 1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0
(c) Correctable single-bit error (d) Uncorrectable error pattern row parity error column parity error
0 1 1 1 0 1 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 1 1 1 1 0 1 0 0 1 1 0 1 1 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 0 1 1 0
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B N f 1 2 1
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ways of choosing k items out of N.
N k ! " # $ % &
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B N N C k N B B j B N j j N k B N N k
B C C B B B C
1 2 1 2 4 3 1 2
= − = −
( ) , ,…
B = BER
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Partial sum 0001 F203 F204 Partial sum 0001 F203 F204 Partial sum F204 F4F5 1E6F9 Partial sum F204 F4F5 1E6F9 Carry E6F9 1 E6FA Carry E6F9 1 E6FA Partial sum E6FA F6F7 1DDF1 Partial sum E6FA F6F7 1DDF1 Carry DDF1 1 DDF2 Carry DDF1 1 DDF2 Ones complement of the result 220D Partial sum DDF2 220D FFFF (a) Checksum calculation by sender (b) Checksum verification by receiver
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– to be appended to message (n bits)
– includes both M and F =>(k+n bits)
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n
n
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– M = 110011, M(X) = X5 + X4 + X + 1, and for G = 11001 we have G(X) = X4 + X3 + 1 – Math is still mod 2
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Figure 6.6 General CRC Architecture to Implement Divisor (1 + A1X + A2X2 + … + An–1Xn–k–1 + Xn–k)
Cn–k–2 C1 C0 An–k–1 An–k–2 A2 A1
Input (k bits) Output (n bits) Switch 1 Switch 2
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cn-1 cn-2 c1 c0 + + + + + ... x x x x
Input Bits
an-1 an-2 a2 a1
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data no error or correctable error detectable but not correctable error codeword
FEC decoder
k bits data codeword
FEC encoder
n bits
Transmitter Receiver Figure 6.8 Error Correction Process
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1 2 3 4 5 6 7 8 9 3 dB 10 11 12 13 14 10–5 10–6 10–4 10–3 10–2 10–1 1 Probability of bit error (BER) (Eb/N0) (dB)
Figure 6.9 How Coding Improves System Performance
2.77 dB
Region of coding gain Without coding Rate 1/2 coding
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