[PPT] - Chapter 5 Digital Design and Computer Architecture , 2 nd Edition PowerPoint Presentation

SLIDE 1

Chapter 5 <1>

Digital Design and Computer Architecture, 2nd Edition

Chapter 5

David Money Harris and Sarah L. Harris

SLIDE 2

Chapter 5 <2>

Chapter 5 :: Topics

Introduction
Arithmetic Circuits
Number Systems
Sequential Building Blocks
Memory Arrays
Logic Arrays

SLIDE 3

Chapter 5 <3>

Digital building blocks:

– Gates, multiplexers, decoders, registers, arithmetic circuits, counters, memory arrays, logic arrays

Building blocks demonstrate hierarchy,

modularity, and regularity:

– Hierarchy of simpler components – Well-defined interfaces and functions – Regular structure easily extends to different sizes

You can use these building blocks to build

a processor (see Chapter 7, CpE 300)

Introduction

SLIDE 4

Chapter 5 <4>

A B 1 1 1 1 S Cout S = Cout =

Half Adder

A B S Cout

+ A B 1 1 1 1 S Cout S = Cout =

Full Adder

Cin 1 1 1 1 1 1 1 1

A B S Cout Cin

+

Review: 1-Bit Adders

SLIDE 5

Chapter 5 <5>

A B 1 1 1 1 1 1 S Cout 1 S = Cout =

Half Adder

A B S Cout

+ A B 1 1 1 1 1 1 S Cout 1 S = Cout =

Full Adder

Cin 1 1 1 1 1 1 1 1 1 1 1 1 1

A B S Cout Cin

+

Review: 1-Bit Adders

SLIDE 6

Chapter 5 <6>

A B 1 1 1 1 1 1 S Cout 1 S = A  B Cout = AB

Half Adder

A B S Cout

+ A B 1 1 1 1 1 1 S Cout 1 S = A  B Cin Cout = AB + ACin + BCin

Full Adder

Cin 1 1 1 1 1 1 1 1 1 1 1 1 1

A B S Cout Cin

+

Review: 1-Bit Adders

SLIDE 7

Chapter 5 <7>

A B S Cout Cin +

N N N

Types of carry propagate adders (CPAs):

– Ripple-carry (slow) – Carry-lookahead (fast) – Prefix (faster) – see book

Carry-lookahead and prefix adders faster for large adders

but require more hardware Symbol

Multibit Adders (CPAs)

SLIDE 8

Chapter 5 <8>

S31 A30 B30 S30 A1 B1 S1 A0 B0 S0 C30 C29 C1 C0 Cout + + + + A31 B31 Cin

Chain 1-bit adders together
Carry ripples through entire chain
Disadvantage: slow

Ripple-Carry Adder

SLIDE 9

Chapter 5 <9>

tripple = NtFA

where tFA is the delay of a 1-bit full adder

Ripple-Carry Adder Delay

SLIDE 10

Chapter 5 <10>

Some definitions:

– Column i produces a carry out by either generating a carry out

r propagating a carry in to the carry out

Carry-Lookahead Adder

SLIDE 11

Chapter 5 <11>

Some definitions:

– Column i produces a carry out by either generating a carry out

r propagating a carry in to the carry out

– Generate (Gi) and propagate (Pi) signals for each column:

Generate: Column i will generate a carry out if Ai AND Bi are

both 1.

Gi = Ai Bi

Carry-Lookahead Adder

SLIDE 12

Chapter 5 <12>

Some definitions:

– Column i produces a carry out by either generating a carry out

r propagating a carry in to the carry out

– Generate (Gi) and propagate (Pi) signals for each column:

Generate: Column i will generate a carry out if Ai AND Bi are

both 1.

Gi = Ai Bi

Propagate: Column i will propagate a carry in to the carry out

if Ai OR Bi is 1.

Pi = Ai + Bi

Carry-Lookahead Adder

SLIDE 13

Chapter 5 <13>

Some definitions:

– Column i produces a carry out by either generating a carry out

r propagating a carry in to the carry out

– Generate (Gi) and propagate (Pi) signals for each column:

Generate: Column i will generate a carry out if Ai AND Bi are

both 1.

Gi = Ai Bi

Propagate: Column i will propagate a carry in to the carry out

if Ai OR Bi is 1.

Pi = Ai + Bi

Carry out: The carry out of column i (Ci) is:

Ci = Gi + Pi Ci-1

Carry-Lookahead Adder

SLIDE 14

Chapter 5 <14>

Some definitions:

– Column i produces a carry out by either generating a carry out

r propagating a carry in to the carry out

– Generate (Gi) and propagate (Pi) signals for each column:

Generate: Column i will generate a carry out if Ai AND Bi are

both 1.

Gi = Ai Bi

Propagate: Column i will propagate a carry in to the carry out

if Ai OR Bi is 1.

Pi = Ai + Bi

Carry out: The carry out of column i (Ci) is:

Ci = Gi + Pi Ci-1 = Ai Bi + (Ai + Bi )Ci-1

Carry-Lookahead Adder

SLIDE 15

Chapter 5 <15>

Compute carry out (Cout) for k-bit blocks using generate and propagate signals

Carry-Lookahead Adder

SLIDE 16

Chapter 5 <16>

Example: 4-bit blocks:

Carry-Lookahead Adder

SLIDE 17

Chapter 5 <17>

Example: 4-bit blocks:

Propagate: P3:0 = P3P2 P1P0

All columns must propagate

Generate: G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 ))

Most significant bit generates or lower bit

propagates a generated carry

Carry-Lookahead Adder

SLIDE 18

Chapter 5 <18>

Example: 4-bit blocks:

Propagate: P3:0 = P3P2 P1P0

All columns must propagate

Generate: G3:0 = G3 + P3 (G2 + P2 (G1 + P1G0 ))

Most significant bit generates or lower bit

propagates a generated carry

Generally,

Pi:j = PiPi-1 Pi-2Pj Gi:j = Gi + Pi (Gi-1 + Pi-1 (Gi-2 + Pi-2Gj ) Ci = Gi:j + Pi:j Cj-1

Carry-Lookahead Adder

SLIDE 19

Chapter 5 <19>

Step 1: Compute Gi and Pi for all columns
Step 2: Compute G and P for k-bit blocks
Step 3: Cin propagates through each k-bit

propagate/generate block

Carry-Lookahead Addition

SLIDE 20

Chapter 5 <20>

S31 A30 B30 S30 A1 B1 S1 A0 B0 S0 C30 C29 C1 C0 Cout + + + + A31 B31 Cin

Chain 1-bit adders together
Carry ripples through entire chain
Disadvantage: slow

Ripple-Carry Adder

tripple = NtFA

SLIDE 21

Chapter 5 <21>

B0 + + + + P3:0 G3 P3 G2 P2 G1 P1 G0 P3 P2 P1 P0 G3:0 Cin Cout A0 S0 C0 B1 A1 S1 C1 B2 A2 S2 C2 B3 A3 S3 Cin A3:0 B3:0 S3:0 4-bit CLA Block Cin A7:4 B7:4 S7:4 4-bit CLA Block C3 C7 A27:24 B27:24 S27:24 4-bit CLA Block C23 A31:28 B31:28 S31:28 4-bit CLA Block C27 Cout

32-bit CLA with 4-bit Blocks

tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

SLIDE 22

Chapter 5 <22>

For N-bit CLA with k-bit blocks:

tCLA = tpg + tpg_block + (N/k – 1)tAND_OR + ktFA

– tpg : delay to generate all Pi, Gi – tpg_block : delay to generate all Pi:j, Gi:j – tAND_OR : delay from Cin to Cout of final AND/OR gate in k-bit CLA block

An N-bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16

Carry-Lookahead Adder Delay

SLIDE 23

Chapter 5 <23>

Compare delay of 32-bit ripple-carry and carry-lookahead adders

CLA has 4-bit blocks
2-input gate delay = 100 ps; full adder delay = 300 ps
Ripple
𝑢𝑠𝑗𝑞𝑞𝑚𝑓 = 𝑂𝑢𝐺𝐵 = 32 300 = 9.6 ns
Carry-lookahead
𝑢𝐷𝑀𝐵 = 𝑢𝑞𝑕 + 𝑢𝑞𝑕_𝑐𝑚𝑝𝑑𝑙 + 𝑂/𝑙 − 1 𝑢𝐵𝑂𝐸_𝑃𝑆 + 𝑙 𝑢𝐺𝐵
𝑢𝐷𝑀𝐵 = 100 + 600 + 7 200 + 4 300 = 3.3 ns

Adder Delay Comparisons

AND/OR 6 Gates for 𝐻3:0 3 Gates for 𝐷𝑗𝑜 → 𝐷𝑝𝑣𝑢

SLIDE 24

Chapter 5 <24>

Symbol Implementation

+ A B

Y

Y A B

N N N N N N N

Subtracter

SLIDE 25

Chapter 5 <25>

Symbol Implementation

A3 B3 A2 B2 A1 B1 A0 B0 Equal

=

A B Equal

4 4

Comparator: Equality

SLIDE 26

Chapter 5 <26>

Q CLK Reset

N + N 1

CLK Reset

N N

Q

N r

Symbol Implementation

Increments on each clock edge
Used to cycle through numbers. For example,

– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…

Example uses:

– Digital clock displays – Program counter: keeps track of current instruction executing

Counters

SLIDE 27

Chapter 5 <27>

Q CLK Reset

N + N 1

CLK Reset

N N

Q

N r

Symbol Implementation

Increments on each clock edge
Used to cycle through numbers. For example,

– 000, 001, 010, 011, 100, 101, 110, 111, 000, 001…

Example uses:

– Digital clock displays – Program counter: keeps track of current instruction executing

Counters

SLIDE 28

Chapter 5 <28>

N

Q Sin Sout

Shift a new bit in on each clock edge
Shift a bit out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to

parallel output (Q0:N-1)

Shift Registers

Symbol:

SLIDE 29

Chapter 5 <29>

N

Q Sin Sout

CLK Sin Sout Q0 Q1 QN-1 Q2

Implementation:

Shift a new bit in on each clock edge
Shift a bit out on each clock edge
Serial-to-parallel converter: converts serial input (Sin) to