Chapter 5 Digital Design and Computer Architecture , 2 nd Edition - PowerPoint PPT Presentation

Chapter 5 Digital Design and Computer Architecture , 2 nd Edition David Money Harris and Sarah L. Harris Chapter 5 <1>

Chapter 5 :: Topics • Introduction • Arithmetic Circuits • Number Systems • Sequential Building Blocks • Memory Arrays • Logic Arrays Chapter 5 <2>

Introduction • Digital building blocks: – Gates, multiplexers, decoders, registers, arithmetic circuits, counters, memory arrays, logic arrays • Building blocks demonstrate hierarchy, modularity, and regularity: – Hierarchy of simpler components – Well-defined interfaces and functions – Regular structure easily extends to different sizes • You can use these building blocks to build a processor (see Chapter 7, CpE 300) Chapter 5 <3>

Review: 1-Bit Adders Half Full Adder Adder A B A B C out C out C in + + S S A B C out S C in A B C out S 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 1 0 1 1 1 0 0 1 0 1 S = 1 1 0 C out = 1 1 1 S = C out = Chapter 5 <4>

Review: 1-Bit Adders Half Full Adder Adder A B A B C out C out C in + + S S A B C out S C in A B C out S 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 S = 1 1 0 1 0 C out = 1 1 1 1 1 S = C out = Chapter 5 <5>

Review: 1-Bit Adders Half Full Adder Adder A B A B C out C out C in + + S S C out S A B C in A B C out S 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 S = A  B 1 1 0 1 0 C out = AB 1 1 1 1 1 S = A  B  C in C out = AB + AC in + BC in Chapter 5 <6>

Multibit Adders (CPAs) • Types of carry propagate adders (CPAs): – Ripple-carry (slow) – Carry-lookahead (fast) – Prefix (faster) – see book • Carry-lookahead and prefix adders faster for large adders but require more hardware Symbol A B N N C out C in + N S Chapter 5 <7>

Ripple-Carry Adder • Chain 1-bit adders together • Carry ripples through entire chain • Disadvantage: slow A 31 B 31 A 30 B 30 A 1 B 1 A 0 B 0 C out C in + + + + C 30 C 29 C 1 C 0 S 31 S 30 S 1 S 0 Chapter 5 <8>

Ripple-Carry Adder Delay t ripple = Nt FA where t FA is the delay of a 1-bit full adder Chapter 5 <9>

Carry-Lookahead Adder • Some definitions: – Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out Chapter 5 <10>

Carry-Lookahead Adder • Some definitions: – Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out – Generate ( G i ) and propagate ( P i ) signals for each column: • Generate: Column i will generate a carry out if A i AND B i are both 1. G i = A i B i Chapter 5 <11>

Carry-Lookahead Adder • Some definitions: – Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out – Generate ( G i ) and propagate ( P i ) signals for each column: • Generate: Column i will generate a carry out if A i AND B i are both 1. G i = A i B i • Propagate: Column i will propagate a carry in to the carry out if A i OR B i is 1. P i = A i + B i Chapter 5 <12>

Carry-Lookahead Adder • Some definitions: – Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out – Generate ( G i ) and propagate ( P i ) signals for each column: • Generate: Column i will generate a carry out if A i AND B i are both 1. G i = A i B i • Propagate: Column i will propagate a carry in to the carry out if A i OR B i is 1. P i = A i + B i • Carry out: The carry out of column i ( C i ) is: C i = G i + P i C i-1 Chapter 5 <13>

Carry-Lookahead Adder • Some definitions: – Column i produces a carry out by either generating a carry out or propagating a carry in to the carry out – Generate ( G i ) and propagate ( P i ) signals for each column: • Generate: Column i will generate a carry out if A i AND B i are both 1. G i = A i B i • Propagate: Column i will propagate a carry in to the carry out if A i OR B i is 1. P i = A i + B i • Carry out: The carry out of column i ( C i ) is: C i = G i + P i C i-1 = A i B i + ( A i + B i ) C i-1 Chapter 5 <14>

Carry-Lookahead Adder Compute carry out ( C out ) for k -bit blocks using generate and propagate signals Chapter 5 <15>

Carry-Lookahead Adder • Example: 4-bit blocks: Chapter 5 <16>

Carry-Lookahead Adder • Example: 4-bit blocks: Propagate: P 3:0 = P 3 P 2 P 1 P 0 • All columns must propagate Generate: G 3:0 = G 3 + P 3 ( G 2 + P 2 ( G 1 + P 1 G 0 )) • Most significant bit generates or lower bit propagates a generated carry Chapter 5 <17>

Carry-Lookahead Adder • Example: 4-bit blocks: Propagate: P 3:0 = P 3 P 2 P 1 P 0 • All columns must propagate Generate: G 3:0 = G 3 + P 3 ( G 2 + P 2 ( G 1 + P 1 G 0 )) • Most significant bit generates or lower bit propagates a generated carry • Generally, P i : j = P i P i -1 P i -2 P j G i : j = G i + P i ( G i -1 + P i -1 ( G i -2 + P i -2 G j ) C i = G i:j + P i:j C j-1 Chapter 5 <18>

Carry-Lookahead Addition • Step 1: Compute G i and P i for all columns • Step 2: Compute G and P for k -bit blocks • Step 3: C in propagates through each k -bit propagate/generate block Chapter 5 <19>

Ripple-Carry Adder • Chain 1-bit adders together • Carry ripples through entire chain • Disadvantage: slow A 31 B 31 A 30 B 30 A 1 B 1 A 0 B 0 C out C in + + + + C 30 C 29 C 1 C 0 S 31 S 30 S 1 S 0 t ripple = Nt FA Chapter 5 <20>

32-bit CLA with 4-bit Blocks B 31:28 A 31:28 B 27:24 A 27:24 B 7:4 A 7:4 B 3:0 A 3:0 C 27 C 23 C 7 C 3 4-bit CLA 4-bit CLA 4-bit CLA 4-bit CLA C out C in Block Block Block Block S 31:28 S 27:24 S 7:4 S 3:0 B 3 A 3 B 2 A 2 B 1 A 1 B 0 A 0 C 2 C 1 C 0 C in + + + + S 3 S 2 S 1 S 0 G 3:0 G 3 P 3 G 2 P 2 G 1 P 1 G 0 P 3 P 3:0 C out P 2 P 1 C in P 0 t CLA = t pg + t pg_ block + ( N/k – 1) t AND_OR + kt FA Chapter 5 <21>

Carry-Lookahead Adder Delay For N -bit CLA with k -bit blocks: t CLA = t pg + t pg_ block + ( N/k – 1) t AND_OR + kt FA – t pg : delay to generate all P i , G i – t pg_ block : delay to generate all P i : j , G i : j – t AND _ OR : delay from C in to C out of final AND/OR gate in k -bit CLA block An N -bit carry-lookahead adder is generally much faster than a ripple-carry adder for N > 16 Chapter 5 <22>

Adder Delay Comparisons Compare delay of 32-bit ripple-carry and carry-lookahead adders • CLA has 4-bit blocks • 2-input gate delay = 100 ps; full adder delay = 300 ps • Ripple • 𝑢 𝑠𝑗𝑞𝑞𝑚𝑓 = 𝑂𝑢 𝐺𝐵 = 32 300 = 9.6 ns • Carry-lookahead • 𝑢 𝐷𝑀𝐵 = 𝑢 𝑞𝑕 + 𝑢 𝑞𝑕_𝑐𝑚𝑝𝑑𝑙 + 𝑂/𝑙 − 1 𝑢 𝐵𝑂𝐸_𝑃𝑆 + 𝑙 𝑢 𝐺𝐵 • 𝑢 𝐷𝑀𝐵 = 100 + 600 + 7 200 + 4 300 = 3.3 ns 6 Gates 3 Gates for AND/OR for 𝐻 3:0 𝐷 𝑗𝑜 → 𝐷 𝑝𝑣𝑢 Chapter 5 <23>

Subtracter Symbol Implementation A B N A B N N N N - + N N Y Y Chapter 5 <24>

Comparator: Equality Symbol Implementation A 3 B 3 A 2 A B 4 4 B 2 Equal = A 1 B 1 Equal A 0 B 0 Chapter 5 <25>

Counters • Increments on each clock edge • Used to cycle through numbers. For example, – 000, 001, 010, 011, 100, 101, 110, 111, 000, 001… • Example uses: – Digital clock displays – Program counter: keeps track of current instruction executing Implementation Symbol CLK CLK N N N Q + Q r N N 1 Reset Reset Chapter 5 <26>

Counters • Increments on each clock edge • Used to cycle through numbers. For example, – 000, 001, 010, 011, 100, 101, 110, 111, 000, 001… • Example uses: – Digital clock displays – Program counter: keeps track of current instruction executing Implementation Symbol CLK CLK N N N Q + Q r N N 1 Reset Reset Chapter 5 <27>

Shift Registers • Shift a new bit in on each clock edge • Shift a bit out on each clock edge • Serial-to-parallel converter : converts serial input ( S in ) to parallel output ( Q 0: N -1 ) Symbol: N Q S in S out Chapter 5 <28>

Shift Registers • Shift a new bit in on each clock edge • Shift a bit out on each clock edge • Serial-to-parallel converter : converts serial input ( S in ) to parallel output ( Q 0: N -1 ) Symbol: Implementation: CLK N Q S in S out S in S out Q 0 Q 1 Q 2 Q N-1 Chapter 5 <29>