Chapter 5 Structural Specification of Hardware Part2 1 - - PowerPoint PPT Presentation

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Chapter 5 Structural Specification of Hardware Part2 1 - - PowerPoint PPT Presentation

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Chapter 5 Structural Specification of Hardware Part2 1 benyamin@mehr.sharif.edu 4-Bit Comparator Design b3 a3 b0 a0 b2 a2 b1 a1 A A A A A>B A>B A>B A>B B B B B A=B A=B A=B A=B > > > > = = = =

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Chapter 5

Structural Specification of Hardware Part2

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4-Bit Comparator Design

A B > = < A>B A=B A<B A B > = < A>B A=B A<B A B > = < A>B A=B A<B A B > = < A>B A=B A<B b3 a3 b2 a2 b1 a1 b0 a0

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4-Bit Comparator Entity Declaration

Entity nibble_comparator IS PORT( a,b:IN BIT_VECTOR(3 downto 0); gt,eq,lt: IN BIT; a_gt_b, a_eq_b, a_lt_b : OUT BIT ); END;

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4-Bit Comparator Architecture Declaration

Architecture iterative1 OF nibble_comparator IS SIGNAL im:BIT_VECTOR(0 TO 8); BEGIN

c0:ENTITY WORK.bit_comparator PORT MAP (a(3),b(3),gt,eq,lt,im(0),im(1),im(2)); c1TOc2:FOR i in 1 to 2 GENERATE c:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; c3:ENTITY WORK.bit_comparator PORT MAP (a(0),b(0),im(6),im(7),im(8),a_gt_b,a_eq_b,a_lt_b);

END;

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Association List of Generate Statement

PORT MAP ( a(i) , b(i) ,im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2) ); a(1) b(1) im(0) im(1) im(2) im(3) im(4) im(5) a(2) b(2) im(3) im(4) im(5) im(6) im(7) im(8) i=1 i=2

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Generate Statement Syntax Detail

c1TOc2: FOR i IN 1 TO 2 GENERATE c:ENTITY WORK.bit_comparator PORT MAP ((a(i),b(i),im(3*i-3),im(3*i-2),im(3*i- 1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE;

generate_lable : FOR generation_scheme GENERATE concurrent_statements END GENERATE;

generation lable Generation scheme id IN x TO y Id IN y DOWNTO x concurrent statement

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More on Iterative Hardware

Architecture iterative2 OF nibble_comparator IS CONSTANT n : INTEGER:=4; SIGNAL im:BIT_VECTOR(0 TO 3*(n-1)-1 ); BEGIN call:FOR i in n-1 downto 0 GENERATE IF i=n-1 GENERATE most:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),gt,eq,lt,im(0),im(1),im(2)); END GENERATE; IF i>0 AND i<n-1 GENERATE rest:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),im(3*i-3),im(3*i-2),im(3*i-1),im(3*i+0),im(3*i+1),im(3*i+2)); END GENERATE; IF i=0 GENERATE least:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i), im(3*(n-1)-3),im(3*(n-1)-2),im(3*(n-1)-1),a_gt_b,a_eq_b,a_lt_b); END GENERATE; END GENERATE; END;

Constant Declaration

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IF Generate Syntax Detail

IF condition GENERATE concurrent statements END GENERATE

IF i=n-1 GENERATE most:ENTITY WORK.bit_comparator PORT MAP (a(i),b(i),gt,eq,lt,im(0),im(1),im(2)); END GENERATE;

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More On Iterative Hardware

Entity reg8 IS

PORT(di:IN BIT_VECTOR(7 downto0); clk:IN BIT;qo:OUT BIT_VECTOR(7 downto 0)); END; ARCHITECTURE iterative OF reg8 IS BEGIN g: FOR I in di’RANGE GENERATE g07:ENTITY WORK.latch PORT MAP(di(i),clk,qo(i)); END GENERATE; END;

‘RANGE is an attribute for signals that returns 7 downto 0

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Modeling a Test Bench

  • 1. Provides stimuli to the input ports of the

entity

  • 2. Test bench must contain the circuit under

test

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nibble_comparator Test Bench

ENTITY Test IS END; ARCHITECTURE test OF test IS SIGNAL a,b,gtr,less,eql:BIT; SIGNAL gnd:BIT:=‘0’; SIGNAL vdd:BIT:=‘1’; BEGIN comp:ENTITY WORK.nibble_comparator(iterative2) PORT MAP (a,b,gnd,vdd,’0’,gtr,eql,lss); a<=“0000”,”1111” AFTER 50 ns, “1110” AFTER 150 ns; b<=“0000”,”1110” AFTER 150 ns, “1111” AFTER 250 ns; END;

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OPEN Keyword

  • outputs of a component could be OPEN

A B > = < A>B A=B A<B

OPEN

comp:ENTITY WORK.nibble_comparator(iterative2) PORT MAP (a,b,gnd,vdd,’0’,OPEN,eql,lss);

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OUT vs. BUFFER

Entity ex IS PORT( a: IN BIT; m: IN BIT; b: OUT BIT; c: BUFFER BIT; ); END; ARCHITECTURE sample OF ex IS BEGIN c<=m AND a; b<= NOT a WHEN c=‘1’; END;

BUFFER OUT

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Formal Specification Details

FOR lables : compe_name USE ENTITY Library.EntityName(ArchName) PORT MAP (association_list);

Component COMPONENT n2 IS PORT(m,n:IN BIT;s:OUT BIT); END COMPONENT; FOR ALL:n2 USE Entity WORK.nand2(single) PORT MAP (x,y,z); C0: n2 port map (a,b,z);

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m n s x y z

Formal Specification Details

i1 i2 o1 a b c Actual signals Local ports Component ports Formal ports

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Chapter 6

Design Organization and Parameterization

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Design Organization and Parameterization

  • Subprograms
  • Parameterizing and customizing design
  • Definition and usage of library packages
  • Generic design
  • Design configuration
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Definition and Usage of Subprograms

  • Simplify coding
  • Modularity
  • Readability
  • Functions

– Cannot alter the values of their parameters – Return a value

  • Procedures

– Used as a statement – Can alter the values of its parameters

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Function Declaration

  • Subprograms can be declared in architecture

declarative part or packages

  • Each function must have return expression
  • All formal parameters are considered IN mode

FUNCTION func_name (formal_parameter_list) RETURN return_type IS function_declarative_part variable and constant declaration

BEGIN sequential statements –including RETURN statement; END func_name;

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Functional Single-Bit Comparator

Architecture functional OF bit_comparator IS

FUNCTION fgl(w,x,gl:BIT) RETURN BIT IS BEGIN RETURN (w AND gl) OR (NOT x AND gl) OR (w AND NOT x); END fgl; FUNCTION feq(w,x,eq:BIT) RETURN BIT IS BEGIN RETURN (w AND x AND eq) OR (NOT w AND NOT x AND eq); END feq; BEGIN a_gt_b<=fgl(a,b,gt) AFTER 12 NS; a_eq_b<=feq(a,b,eq) AFTER 12 NS; a_lt_b <=fgl(b,a,lt) AFTER 12 NS; END;

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Concurrent Statements

Signal assignment Component instantiation

  • Process statement

Concurrent procedure call

  • Block statement

Generate statement

  • Assertion statement
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Sequential Statements

Signal assignment statement Variable assignment statement

  • Wait statement

If,case,loop statement

  • Procedure call statement
  • Exit,return statement
  • Assertion statement
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Variable Declaration

Examples:

VARIABLE a :BIT ; VARIABLE x : BIT := ‘1’; VARIABLE x,y,z : BIT_VECTOR(1 to 4) := “1011” ; VARIABLE b,i :INTEGER := -10; VARIABLE flag : BOOLEAN := TRUE;

VARIABLE identifier_list : type [:= init_value] ;

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Variable Assignment

Target_variable := expression A := b AND c; A := c; X := (b and c) XOR b; i := i+1; Z := a*b+c/2-(w*t);

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Control Statements

If-else statement

  • Case statement

For-loop statement While-loop statement

  • Exit statement
  • Next statement
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IF Statement

IF condition THEN sequential statements; END IF; IF condition THEN statements; ELSE statements; END IF; IF condition THEN statements; ELSIF condition THEN statements; ELSIF condition THEN statements; ELSE statements; END IF;

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IF Statement Example

IF sel=‘1’ THEN z<=i1; ELSE z<=i2; END IF; IF sel=‘1’ THEN z<=i1; ELSIF sel=‘0’ THEN z<=i2; ELSE w<=‘0’ END IF;

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FOR LOOP Statement

Range ::= x TO y x<y | y DOWNTO x x<y | id’RANGE id is signal

FOR loop_counter IN Range LOOP sequential statements; END LOOP;

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FOR LOOP Example

SIGNAL a:BIT_VECTOR(10 downto 0); SIGNAL b:BIT_VECTOR(0 to 10); …. b’RANGE FOR k IN 0 to 10 LOOP a(k)<=b(10-k); END LOOP;

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WHILE LOOP Statement

WHILE condition LOOP sequential statements; END LOOP;

  • Loop will continue until condition becomes FALSE
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WHILE LOOP Example

WHILE Enable=‘1’ LOOP z<=‘1’; WAIT for 10 ns; z<=‘0’; WAIT for 10 ns; END LOOP; PULSE Generator Enable z

20 ns

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Procedure Call Declaration

  • Default class for inputs of subprograms are CONSTANT
  • Default class for outputs of subprograms are VARIABLE
  • In procedure declaration all input and outputs must be

declared explicitly

PROCEDURE proc_name (formal_parameter_list) IS procedure_declarative_part

BEGIN sequential statements END proc_name;

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Procedure Call Example

PROCEDURE bin2int(bin:IN BIT_VECTOR(7 downto 0); int:OUT INTEGER) IS VARIABLE result:INTEGER; BEGIN result:=0; FOR i IN bin’RANGE LOOP IF bin(i)=‘1’ THEN result:=result+2**I; END IF; END FOR; END bin2int;

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Unconstrained Array

  • Range section of an array can be omitted
  • Range will be determined in compiled time

when an actual parameter is used

PROCEDURE bin2int(bin:IN BIT_VECTOR;int:OUT INTEGER) IS …. END; … SIGNAL i:INTEGER; SIGNAL a:BIT_VECTOR(12 DOWNTO 1); … bin2int( a , I );

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General bin2int Procedure

PROCEDURE bin2int(bin:IN BIT_VECTOR;int:OUT INTEGER) IS

VARIABLE result:INTEGER; BEGIN result:=0; FOR i IN bin’RANGE LOOP IF bin(i)=‘1’ THEN result:=result+2**I; END IF; END FOR; END bin2int;

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ApplyData Procedure Call

TYPE integers IS ARRAY (0 to 12) OF INTEGER; PROCEDURE apply_data(SIGNAL target:OUT BIT_VECTOR(3 downto 0); CONSTANT values: IN integers;CONSTANT period: IN TIME) IS VARIABLE j:INTEGER; VARIABLE tmp,pos:INTEGER:=0; VARIBALE buf:BIT_VECTOR(3 DOWNTO 0); BEGIN FOR I IN 0 TO 12 LOOP tmp:=values(i); j:=0; WHILE j<=3 LOOP IF(tmp MOD 2 =1) THEN buf(j):=‘1’; ELSE buf(j):=‘0’; END IF; tmp:=tmp/2; j:=j+1; END LOOP; target<=TRANSPORT buf AFTER i*period; END LOOP; END apply_data;

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nibble_comparator Test Bench Using apply_data

ARCHITECTURE procedural OF nibble_comparator IS TYPE integers IS ARRAY (0 to 12) OF INTEGER; PROCEDURE apply_data(SIGNAL target:OUT BIT_VECTOR(3 downto 0); CONSTANT values: IN integers;CONSTANT period: IN TIME) IS … END apply_data; SIGNAL a,b:BIT_VECTOR(3 DOWNTO 0); SIGNAL eql,lss,gtr:BIT; BEGIN a1:ENTITY WORK.nibble_comparator PORT MAP(a,b,’0’,’1’,’0’,gtr,eql,lss); apply_data(a,00&15&15&14&14&14&14&10&00&15&00&00&15,50 NS); apply_data(b,(00,14,14,15,15,12,,12,12,15,15,15,00,00),50 NS);

END;